Abstract: A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service components are extended to accommodate a number of dual decor commands and functions which make host system facilities directly available to ES application programs by concurrent execution of program operations within both the emulator and host system environments. The EMCU includes mechanisms for performing an initial level security validation operation which allows subsequent trusted verification of user identity when dual decor commands or functions are invoked.

Abstract: A multiprocessor computer system includes a number of processors, each processor having an interrupt mechanism and connecting in common to a system bus over which interrupt requests are communicated. When a processor accepts an interrupt request from another processor, it generates an acknowledge response on the system bus. If such processor contains a previous and pending interrupt request of an equal or higher priority level, it generates a not acknowledge response on the system bus and refuses the interrupt request. At the completion of servicing an interrupt request, each processor places on the system bus, an interrupt completed command including an address identifying such processor, a code designating a priority level to which it has switched and a code indicating that the processor has completing servicing an interrupt request.

Abstract: Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop. The phase offset is due to circuit delays in the phase detector which result in the issuance of simultaneous "pump up" and "pump down" signals, present even during apparent phase lock. A second pair of flip-flops (or a single flip-flop) of the same type used in the phase detector is sampled to obtain a compensating signal which is applied to the reference input of a differential amplifier in the loop filter. Each of the second pair of flip-flops is forced to assume a permanent state (for example, set) such that their respective Q and Q-bar outputs are always representative of the logic voltage levels at the corresponding outputs of the flip-flops in the phase detector from which the "pump up" and "pump down" are sourced.

Abstract: A fault tolerant computer system includes at least two central processing units each having a cache memory and a parity error detector adapted to sense parity errors in blocks of information read from and write to cache and to issue a cache parity read or write error flag if a parity error is sensed. A system bus couples the CPU to a System Control Unit having a parity error correction facility, and a memory bus couples the SCU to a main memory. An error recovery control feature distributed across the CPU, including a Service Processor and the operating system software, is responsive to the sensing of a read parity error flag in a sending CPU and a write parity error flag in a receiving CPU in conjunction with a siphon operation for transferring the faulting block from the sending CPU to main memory via the SCU (in which given faulting block is corrected) and for subsequently transferring the corrected memory block from main memory to the receiving CPU when a retry is instituted.

Abstract: In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.

Abstract: Resolution transforming raster based imaging system where an image is formed by displaying dots arranged along scan lines, scanned by an energization beam, the scan lines having a predetermined resolution and the system is driven by an image bit map having rows with resolution multiple of said predetermined resolution, a subset of the rows being related to the scan lines, bits in rows unrelated to scan lines, and representative of dots to the displayed being displayed as dots offset to a next adjacent scan line and with a size related to the surrounding bit pattern.

Abstract: A local host data processing system operating under the control of a local host operating system includes components of a hosted operating system. The host operating system further include a TCP/IP network protocol stack which couples to the communications facilities of the host system connected to a local area network for communicating with a number of remote host systems. Host and hosted operating systems share the same TCP/IP network protocol stack. A virtual network mechanism is configured within the local host system to be operatively coupled to the host network protocol stack and provide access to well-known port application programs. When so configured, the mechanism functions as another LAN to which the hosted operating system is attached. The mechanism transforms the well-known port identifier of each inbound packet into a non-well-known port identifier in addition to other station address identifier fields.

Abstract: U2G is a software tool that runs on the GCOS-8 operating system and enables it recognize and process the commonly used commands of the UNIX operating system. U2G is a UNIX-GCOS-8 translator that enables the GCOS-8 to recognize, accept and execute UNIX commands. Thus, it enables the UNIX users to work with the GCOS-8 system without prior training. U2G can translate the most commonly used UNIX commands along with their respective options into equivalent GCOS-8 Time Sharing System (TSS) commands. U2G can be used with a "Verbose" mode option which serves to provide descriptive information about the commands and the translation process. U2G has on-line help screens and "explain" pages for all of the important concepts and equivalences. U2G enhances the capabilities of GCOS-8 by supporting the important UNIX concept of "aliasing" and the use of shell variables.

Abstract: U2G is a software tool that runs on the GCOS-8 operating system and enables it recognize and process the commonly used commands of the UNIX operating system. U2G is a UNIX-GCOS-8 translator that enables the GCOS-8 to recognize, accept and execute UNIX commands. Thus, it enables the UNIX users to work with the GCOS-8 system without prior training. U2G can translate the most commonly used UNIX commands along with their respective options into equivalent GCOS-8 Time Sharing System (TSS) commands. U2G can be used with a "Verbose" mode option which serves to provide descriptive information about the commands and the translation process. U2G has on-line help screens and "explain" pages for all of the important concepts and equivalences. U2G enhances the capabilities of GCOS-8 by supporting the important UNIX concept of "aliasing" and the use of shell variables. Further, the UNIX "piping" feature is made available to GCOS-8.

Abstract: A layered communications bridge mechanism connected between an upper communications layer of a first communications layer mechanism executing in a user level process and a layered communication kernel process of a second system corresponding to the next lower layers of the first communications layer mechanism. The bridge includes an upper bridge mechanism operating to appear to the lowest layer or the layers of the first communications layer mechanism to be the next lower layer of the first layered communications mechanism and a lower bridge mechanism operating to appear to the upper communications layer of the second system kernel process to be the next higher layer of the communications layers of the second system and the upper and lower bridge mechanisms operate to map between the operations of the lower layer of the first communications layer mechanism and the upper layer of the layered communications layers of the second system.

Abstract: In a power supply with a boost pre-regulator and power factor correction devices the voltage induced in an auxiliary winding magnetically coupled to the inductor of the pre-regulator and rectified by a diode bridge charges an integrating capacitor, shunted by a discharging resistor, to a voltage which compared with predetermined reference voltages allows to detect and to signal anomalous operative conditions, such as overload or unoperativeness of the power factor correction devices for the execution of suitable intervention procedures.

Abstract: A single device dual action lead forming tool uses standard long nose pliers as the basis of its construction. A set of lead forming elements is incorporated into each plier jaw element. Each set contains forming tooth and forming receptacle elements positioned adjacent to one another in a predetermined manner. The elements of one set are arranged within one jaw element in a reverse order relative to the arrangement of lead forming elements in the other jaw element. When the jaw elements are closed, pairs of like positioned forming tooth and receptacle elements of both sets cooperate together to form both the inner and other leads of a single electronic component in a single operation.

Abstract: An endless ink ribbon cartridge with protected splice of the endless ribbon, wherein a reactance detector element housed in the cartridge at a location close to a predetermined travel path of the ink ribbon increases its reactance as a conductive strip disposed on the ribbon at a predetermined location relative to the splice moves close past the detector element, the reactance increase being detected by a protection arrangement external of the cartridge to prevent printing operations from being carried out through said splice.

Abstract: A computer frame of riveted modular construction, formed by a plurality of essentially flat structural members provided with stiffening ribs which members are formed from zinc plated sheet metal and only joined together by riveting following an additional step of fully zinc plating the individual members, with no need for any further protective and finishing treatments.

Abstract: In order to achieve the integration of a plurality of processors, each capable of directly addressing a limited internal space storage range, with a larger external memory space (e.g., a mass memory), the processors are organized into clusters, each having a plurality of processors and a common secondary cache. Each cluster is assigned a two-bit cluster number. Intermediate a primary cache in each processor and the secondary cache in the cluster, an address translator is provided for effecting transformation between internal memory space addresses and external memory space addresses. The external memory space is divided into areas private to each cluster and shared by all the processors. An internal address indicator bit, in conjunction with the cluster number from a requesting processor primary cache, is employed to set up the transformation either to the private external space of that cluster or the shared external space.

Abstract: In order to increase the information exchange speed among the several transaction members or subsystems organized around a bus carried on a backpanel, all lines of the bus are isolated, using CMOS switches, from the stub to each transaction member which is not instantaneously required for information exchange. The CMOS switches are physically placed as close as practical to the junction of each individual stub to the bus proper. This is achieved by placing the integrated circuits containing the CMOS switches on each subsystem circuit board proximate the male-edge-connector-to-female-edge-connector regions at which the junctions between the bus proper and the stubs are established. Preferably, the CMOS switch integrated circuits are emplaced on the backpanel itself proximate the edge connector regions communicating with each of the subsystems.

Abstract: A method for addressing mass memory in which information is stored in control intervals of physically contiguous disk segments subject to irregularities in the mapping is disclosed. Such irregularities may include discontinuities at some regular interval, which may or may not be 2", and/or offset from zero with respect to a virtual address employed by a user. Within the method, a unique hashing algorithm is employed to convert a virtual address to a physical address taking into account such irregularities in the mapping. This algorithm is particularly characterized by its use of integer binary arithmetic which results in high speed and complete accuracy. For the special and common condition in which discontinuities appearing at some regular interval of 2", a similar disclosed algorithm may be employed to achieve even greater speed of address transformation.

Abstract: A session mirroring facility is utilized in conjunction with the operating system of a host system. The facility captures user input and system output in a way which is transparent to the user whose session is being captured. It can operate in selectable operating modes which allows the monitoring of a session by any number of parties as it is taking place and being recorded and the playing back of the session at some later time by one or more parties.

Abstract: A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler and file management components are extended to accommodate and to to allow creation and access to linked files within both host and emulated system files.

Abstract: Method and apparatus to reduce the number of control words stored in a read only control store of a microprogrammed unit of the CPU of a large scale computer. A set of control fields are required to control the active elements of the unit to cause the unit to execute a large number of different basic operations. Typically the required set of control fields are included in control words stored in a control store controlling the unit during the execution of a basic operation. Obtaining some of the set of required control fields from other sources available within the unit results in a significant reduction in the number of control words stored in the control store without reducing the functionality of the unit.