Abstract: A separate data stream allows encoding of an overlay image, which is to be superimposed on images of a video sequence. The pixels of the overlay image can be transparent or have a text color, a shadow color, or an intermediate color either between the text color and the shadow color, or between the shadow color and the color of the corresponding pixel in the underlying video image. The intermediate colors provide for antialiasing. In addition, a color selection circuit allows selection of the next color from a pool of 9 colors, using a 3-bit field.

Abstract: A digital video compression system and an apparatus implementing this system are disclosed. Specifically, matrices of pixels in the RGB signal format are converted into YUV representation, including a step of selectively sampling the chrominance components. The signals are then subjected to a discrete cosine transform (DCT). A circuitry implementing the DCT in a pipelined architecture is provided. A quantization step eliminates DCT coefficients having amplitude below a set of preset thresholds. The video signal is further compressed by coding the elements of the quantized matrices in a zig-zag manner. This representation is further compressed by Huffman codes. Decompression of the signal is substantially the reverse of compression steps. The inverse discrete cosine transform (IDCT) may be implemented by the DCT circuit. Circuits for implementing RGB to YUV conversion, DCT, quantization, coding and their decompression counterparts are disclosed.

Abstract: A digital video compression system and an apparatus implementing this system are disclosed. Specifically, matrices of pixels in RGB, YUV or CMYK formats are accepted for data compression. The data are rearranged in 8x8 pixel blocks, each block being of one pixel component type. The pixel data are then subjected to a discrete cosine transform (DCT). A quantization step eliminates DCT coefficients having amplitude below a set of preset thresholds. The video signal is further compressed by coding the elements of the quantized matrices in a zig-zag manner. This representation is further compressed by Huffman codes. Decompression of the signal is substantially the reverse of compression steps. The inverse discrete cosine transform (IDCT) may be implemented by the DCT circuit. The circuits may be implemented in a single integrated circuit chip. Three levels of compression rate control are provided during processing of video data.

Abstract: A complementary metal-oxide semiconductor (CMOS) array multiplier cell comprising two CMOS equivalence circuits for sum generation, two pass transistors and an inverter for carry generation, and a multiplier selector built of a matrix of identical selection elements, a single field effect transistor (FET) switch and an inverter. Each of the selection elements consists of an N-channel FET, a P-channel FET and an inverter. Each equivalence circuit utilizes six transistors: four FET's and an inverter. Total cell device count is 31 to 39 transistors, depending on implementation alternatives.