Abstract: Some embodiments provide a hierarchical method of routing nets within a particular region of a circuit layout. Each net has a set of pins. The method initially partitions the particular region into a first set of sub-regions. For each net, the method identifies a first route that connects a group of first-set sub-regions containing the first net's pins; where some of the routes have at least one route-edge that is at least partially diagonal. The method then partitions the sub-regions into a second set of smaller sub-regions. For a first net, the method identifies a propagation of the first-net's first route into the second-set sub-regions based on congestion between the second-set sub-regions. It then adjusts the congestion between the second set sub-regions based on the identified propagation. For a second net, the method then identifies a propagation of the second-net's first route into the second-set sub-regions based on congestion between the second-set sub-regions.

Abstract: A method for modeling a circuit design includes synthesizing the circuit design to create a first gate-level representation of the circuit design. The method also includes analyzing a second gate-level representation of the circuit design to learn architecture information, and resynthesizing the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design. A computer-readable storage medium has stored thereon computer instructions that, when executed by a computer, cause the computer to synthesize a circuit design to create a first gate-level representation of the circuit design.

Abstract: Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

Abstract: Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

Abstract: Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

Abstract: Some embodiments provide a method of producing sub-optimal routes for a net having a set of pins in a region of an integrated-circuit (“IC”) layout. In some embodiments, such a method is used for a router that partitions the region into a plurality of sub-regions. This method initially identifies a first set of sub-regions that contain the net's pins. It then obtains a second set of sub-regions by adding a third set of sub-regions to the first set of sub-regions. Each sub-region in the third set does not contain any pins of the net. For the second set of sub-regions, the method then identifies a first set of routes, where each route traverses the sub-regions in the second set.

Abstract: A machine-learning model may be created to perform integrated circuit layout extraction. Using such a machine-learning system has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. Next, the system performs machine learning using Bayesian inference in order to train the neural network models. The Bayesian inference may be implemented with normal Monte Carlo techniques, Hybrid Monte Carlo techniques, or other Bayesian learning techniques. After the creation of a set of models for each of the smaller simpler extraction problems, the machine-learning based models may be used for extraction.

Abstract: A line driver provides an output signal onto an output. The line driver includes a first current driver coupled to a first terminal of the output. The first current driver is capable of providing a first current to the first terminal that is sufficient to cause an output voltage having a magnitude Y to appear across the output. The first current driver includes a first plurality of elements to provide the first current to the first terminal of the output, each of the plurality of elements having a maximum voltage tolerance that is less than the magnitude Y.

Abstract: A method and system are provided for computing behavioral level observabilities of a digital system. In one example, a logic network is provided for performing an observability analysis at the behavioral level of a digital system. The logic network includes logic objects configured to emulate behavioral observabilities computed from a control data flow graph (CDFG), wherein the logic objects include at least one of: first logic objects configured to compute a token observable condition (TOC) of an edge of the CDFG; and second logic objects configured to compute a node observable condition (NOC) of a node of the CDFG. A logic optimization is used to optimize the logic network to obtain an optimized logic network of the behavioral observabilities.

Abstract: For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A system and method are provided for selectively inferring latch elements in a circuit design from an event-driven hardware description language (HDL) file to an event-independent format. The method includes modeling the file as a plurality of data flow equations, analyzing the plurality of equations for uninitialized variables, and placing a latch at any utilized, uninitialized variable. Control signal information for an inferred latch is also derived during the data flow analysis.

Abstract: Methods and apparatus for modeling noise present in an integrated circuit substrate are disclosed. A position on a surface of the integrated circuit substrate is obtained. A combination of layers associated with the position and defining a vertical column beneath the position is ascertained. A doping profile associated with the combination of layers is obtained. The doping profile includes a plurality of portions, each of which is associated with a different range of substrate depth. Noise in the integrated circuit substrate is then modeled using the obtained doping profile.

Abstract: A system is herein disclosed which allows for the interactive design and analysis of analog and mixed-signal circuits. Circuits may additionally be characterized and verified without leaving the environment provided by the system. The system may be used to analyze multiple circuit designs at the same time. In this manner a designer can create a test that sweeps over several circuit designs. Embodiments of the invention may be integrated with other circuit design tools and development systems.

Abstract: A variable current source model accurately determines timing delays for designs of circuits implemented in integrated circuits. A design for an integrated circuit specifies a resistive-capacitive (“RC”) network. The RC network couples a driving point and a receiving point, and a circuit specified in the design, drives the RC network at the driving point. The variable current source model determines driving currents for the circuit at the driving point based on the RC network and a characterization model of the circuit. A timing delay between the driving point and the receiving point is determined by simulating the drive of the RC network with the driving current at the driving point.

Abstract: A method and apparatus for critical and false path verification takes all the potential false paths and captures the conditions that would make them true paths (or false paths) as a Boolean expression (net list), for the combinational logic only. The net list does not have to be at the gate level, but can be a simplified gate level representation because the verification process is only concerned with the logical behavior, not the actual structure. This allows the simulation to execute more quickly. Since the conditions are only captured between register elements, it can be formally proved whether or not the path can be exercised. If no register value can activate the path, then the analysis is done. Otherwise, a simulation is performed to determine whether the register values required to active the condition actually occur. If the Boolean condition can be satisfied, the simulation is performed on the sequential logic to justify those values.

Abstract: The present invention introduces several methods for implementing integrated circuits that use gridless non Manhattan routing to connect the integrated circuit components. In one embodiment, the non Manhattan routed integrated circuits are created by creating an initial route and then compacting the design down. In another embodiment, a gridless non Manhattan integrated circuits are implemented by adapting a gridless Manhattan routing system into a gridless non Manhattan routing system by rotating a plane of a tile based maze router.

Abstract: An output buffer includes an output stage that includes a transconductance device configured to drive a capacitive load, and a first capacitor coupled to an input of the transconductance device. A converter converts an input clock signal into a current that is provided to charge the first capacitor during a specified interval. The converter includes a feedback loop to adjust the current so as to produce a specified logic level at the specified interval. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method for diagnosing failures within an integrated circuit where known diagnostic fault simulators are unable to detect failure mechanisms which do not conform to known failure models. Basic boolean equations are used to describe the internal nodes forming the logic. These equations are then evaluated by way of a good machine simulation to determine which of the equations are (most) true for failing test patterns and (most) false for passing patterns. At the end of the good machine simulation a score is calculated to determine the number of times (or percentage) for which the equation is true for failing patterns and false for passing patterns. The method is particularly effective for finding shorted nets pairs in which the failure mechanism does not fall within known models. The method described is instrumental in greatly reducing the time required for manual analysis of failure mechanisms not conforming to known models.

Abstract: From a circuit diagram, an electrically connected circuit diagram network is selected. From a layout representing the circuit diagram, an electrically connected layout network is selected that represents the circuit diagram network. A first electrical terminal connection of a first component is selected that connects the first component with the circuit diagram network or with the layout network. A second electrical terminal connection of a second component is selected that connects the component with the circuit diagram network or with the layout network. A first electrical moment is calculated for the transmission path of the layout. A second moment of the corresponding transmission path of the circuit diagram is calculated. A relationship between the first moment and the second moment is predetermined. A value of a resistor or a value of the capacitor of the circuit diagram is now modified in such a way that the relationship is satisfied.