Patents Assigned to Cadence Design System, Inc.
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Patent number: 6651233Abstract: One embodiment of the invention is a recursive partitioning method that place circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots) for a net in the region, the method then identifies the set of sub-regions (i.e., the set slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.Type: GrantFiled: December 19, 2000Date of Patent: November 18, 2003Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6651235Abstract: An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition.Type: GrantFiled: October 30, 2001Date of Patent: November 18, 2003Assignee: Cadence Design Systems, Inc.Inventors: Wei-Jin Dai, Kit-Lam Cheong, Hsi-Chuan Chen, Wei-Lun Kao
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Patent number: 6651237Abstract: A technique for constructing a balanced H-Tree clock layout suited for application to clock signals in integrated circuits, but applicable to other signals requiring balanced distribution over a wide area, involves routing clock wires in a circuit design wherein internal circuit blocks are divided, to the extent possible, into groups having an equal number of circuit blocks. An upper H-Tree clock layout structure is established using the center of mass of each of the circuit block groups as guideposts. Adjustments in wire length to balance the wires of the H-Tree layout. A lower H-Tree clock layout structure is established using center points between pairs of adjacent or nearby circuit blocks as guideposts for the endpoints of clock wires, and then routing, to the extent necessary, wire segments to the individual circuit blocks.Type: GrantFiled: January 18, 2001Date of Patent: November 18, 2003Assignee: Cadence Design Systems, Inc.Inventors: Laurence H. Cooke, Kumar Venkatramani
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Patent number: 6636839Abstract: An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a shooting method to form a non-linear system of equations for initial conditions of the circuit that directly result in the periodic steady state response; 2) solving the non-linear system via a Newton iterative method, where each iteration of the Newton method involves solution of a respective linear system of equations; and 3) for each iteration of the Newton method, solving the respective linear system of equations associated with the iteration of the Newton method via an iterative technique. The iterative technique may be a matrix-implicit application of a Krylov subspace technique, resulting in a computational cost that grows approximately in a linear fashion with the number of nodes in the circuit.Type: GrantFiled: September 5, 2000Date of Patent: October 21, 2003Assignee: Cadence Design Systems, Inc.Inventors: Ricardo Telichevesky, Kenneth S. Kundert, Jacob K. White
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Patent number: 6637018Abstract: A method and apparatus for the synthesis of electronic circuits is described herein. More particularly, the system supports the synthesis of both analog-only, and mixed digital/analog circuitry. The circuit designers knowledge is reused to effect the simulation of mixed analog and digital circuitry, determining data points and curve-fitting the data points to determine a model that closely approximates the simulated circuit performance. The model describes the parameterization of circuit features with respect to circuit performance. The parameterization is used to develop a behavioral model of the circuit that does not retain any of the physical description of the circuit.Type: GrantFiled: October 26, 2000Date of Patent: October 21, 2003Assignee: Cadence Design Systems, Inc.Inventor: Michael J. Demler
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Patent number: 6631470Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: March 23, 2001Date of Patent: October 7, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6631504Abstract: A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e.g., an IEEE standard 1149.1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks preferably comprises a socket access port controller, and test operation is transferred downward and upwards within said hierarchical structure by communicating from a test control circuit block to the test control circuit block at the immediately higher or immediately lower level in the hierarchical structure. Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical.Type: GrantFiled: April 19, 2001Date of Patent: October 7, 2003Assignee: Cadence Design Systems, IncInventors: Bulent Dervisoglu, Laurence H. Cooke
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Patent number: 6629293Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: February 23, 2001Date of Patent: September 30, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6625780Abstract: A system and method for protecting circuit designs from unauthorized use involves techniques for watermarking by embedding a hidden, recognizable input/output signature or code into the circuit design. An internal sequential function, such as a finite state machine, within the circuit design is used to generate a predictable output sequence when a known input sequence is applied. The free input configurations in the internal sequential function of the circuit design are identified and modified to generate the desired output sequence when the known input sequence is applied. A path among the free input configurations is selected, with output values in the desired output sequence being assigned the various state transitions. If there are not enough free input configurations to meet specified watermarking robustness criteria, then additional free input configurations may be added by, for example, adding one or more inputs, outputs or states to the finite state machine.Type: GrantFiled: February 28, 2000Date of Patent: September 23, 2003Assignee: Cadence Design Systems, Inc.Inventors: Edoardo Charbon, Ilhami H. Torunoglu
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Patent number: 6625611Abstract: The mechanism is directed towards method and apparatus for representing multidimensional data. Some embodiments of the invention provide a two-layered data structure to store multidimensional data tuples that are defined in a multidimensional data space. These embodiments initially divide the multidimensional data space into a number of data regions, and create a data structure to represent this division. For each data region, these embodiments then create a hierarchical data structure to store the data tuples within each region. In some of these embodiments, the multidimensional data tuples are spatial data tuples that represent spatial or geometric objects, such as points, lines, polygons, regions, surfaces, volumes, etc. For instance, some embodiments use the two-layered data structure of the invention to store data relating to geometric objects (such as rectangles) that represent interconnect lines of an IC in an IC design layout.Type: GrantFiled: March 15, 2000Date of Patent: September 23, 2003Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Tom Kronmiller, Andrew F. Siegel
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Patent number: 6622291Abstract: A feasible floorplan of a circuit is determined and budgeted in the early phases of circuit design. The process of determining the floorplan and budget includes estimating RTL complexity, physical partitioning, block placement, block i/o placement and top level global routing, and verifying feasibility of the floorplan. Allocation of global timing constraints to each block is performed by producing logic cones representing timing of circuit paths in each block. The circuit paths are optimized to determine a feasible timing for each block. The global constraints are allocated proportionally to each block based on the feasible timing for each block.Type: GrantFiled: October 30, 2000Date of Patent: September 16, 2003Assignee: Cadence Design Systems, Inc.Inventor: Arnold Ginetti
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Patent number: 6622290Abstract: A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.Type: GrantFiled: October 3, 2000Date of Patent: September 16, 2003Assignee: Cadence Design Systems, Inc.Inventors: Arnold Ginetti, Mark Steven Hahn, Harish Kriplani, Naser Awad
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Patent number: 6618849Abstract: Some embodiments of the invention provide a method that identifies a set of routes for a net that has a set of pins in a region of a design layout. The method initially partitions the region into a number of sub-regions. It then identifies a first set of sub-regions that contains the net's pins. The method next determines whether a storage structure stores a set of routes for the identified first set of sub-regions. If so, the method retrieves the set of routes. If not, the method generates a set of routes. In some embodiments, the method generates a set of routes by first identifying a connection set of sub-regions that when combined with the first set forms a closed set of sub-regions. The closed set of sub-regions does not have any sub-region that is not adjacent to another sub-region in the closed set. The storage structure stores a set of routes for the closed set.Type: GrantFiled: January 13, 2002Date of Patent: September 9, 2003Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Heng-Yi Chao
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Patent number: 6618826Abstract: A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described. With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences so that when they are applied, all outputs of embedded RAMs attain known values.Type: GrantFiled: October 26, 2000Date of Patent: September 9, 2003Assignee: Cadence Design Systems, Inc.Inventors: Xinghao Chen, Joseph C. Watkins
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Patent number: 6618837Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.Type: GrantFiled: September 14, 2000Date of Patent: September 9, 2003Assignee: Cadence Design Systems, Inc.Inventors: Xisheng Zhang, Hancheng Liang, Zhihong Liu, Jianhe Guo
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Publication number: 20030159121Abstract: A buffer for use in a logic circuit comprises input and output nodes. A first inverter having a first device size is coupled to the input node. A second inverter is coupled in series with the first inverter and with the output node. The second inverter having a second device size at least six times greater than the first device size. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).Type: ApplicationFiled: February 19, 2002Publication date: August 21, 2003Applicant: Cadence Design Systems, Inc.Inventor: Kenneth Hing Key Tseng
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Patent number: 6608860Abstract: An improved transmitter capable of achieving high linearity with minimal power dissipation is disclosed, comprising a digital phase splitter and an output stage. The digital phase splitter includes a positive phase digital-to-analog converter (DAC) for converting the positive phase portion of a set of input digital data into an analog signal, and a negative phase DAC for converting the negative phase portion of the set of input digital data into another analog signal. The analog signals from the phase splitter are passed to the output stage for transmission onto a transmission medium. The transmitter may be operated in low power dissipation mode. Because the phases of the input digital signal are split in the digital domain prior to the output stage, the output stage experiences minimal crossover distortion. Consequently, the transmitter is able to minimize power dissipation without suffering from poor linearity performance.Type: GrantFiled: November 5, 1999Date of Patent: August 19, 2003Assignee: Cadence Design Systems, Inc.Inventors: Eric H. Naviasky, Martin J. Mengele
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Patent number: 6594800Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: July 15, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6594799Abstract: A multi-faceted portal site acts as a server in the context of an n-tier client/server network, and connects electronic designers and design teams to design and verification tool and service providers on the other through a single portal site. Tools and services accessible to users through the portal site include electronic design automation (EDA) software tools, electronic component information, electronic component databases of parts (or dynamic parts), computing and processing resources, virtual circuit blocks, design expert assistance, and integrated circuit fabrication. Such tools and services may be provided in whole or part by suppliers connected to the portal site. Users accessing the portal site are presented with options in a menu or other convenient format identifying the tools and services available, and are able to more rapidly complete circuit designs by having access to a wide variety of tools and services in a single locale.Type: GrantFiled: February 28, 2000Date of Patent: July 15, 2003Assignee: Cadence Design Systems, Inc.Inventors: William H. Robertson, James M. Plymale
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Publication number: 20030131327Abstract: A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e.g., an IEEE standard 1149.1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks preferably comprises a socket access port controller, and test operation is transferred downward and upwards within said hierarchical structure by communicating from a test control circuit block to the test control circuit block at the immediately higher or immediately lower level in the hierarchical structure. Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical.Type: ApplicationFiled: December 20, 2002Publication date: July 10, 2003Applicant: Cadence Design Systems, Inc.Inventors: Bulent Dervisoglu, Laurence H. Cooke