Abstract: The present disclosure relates to a method for minimizing constraints in the formal verification of an integrated circuit design. The method may include obtaining an unisolated list of constraints initially comprising all known constraints for the integrated circuit design and obtaining an isolated list of constraints initially comprising none of the known constraints. The method may further include attempting to prove an assertion without the known constraints and determining if the assertion is valid. The method may further include updating the isolated list of constraints.

Abstract: Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.

Abstract: Double patterning is achieved with a single reticle while maintaining the integrity of in-scribe patterns and without blading the reticle. In-scribe structures may or may not be double patterning. For example, elements such as electrical test structures might have features that are so closely spaced that double pattering is desired. However, elements such as optical alignment marks might not require double patterning. For those elements for which double patterning is not desired, a first sub-array of the reticle has a pattern for the element, whereas the corresponding location in a second sub-array has a blank. By the corresponding location, it is meant the location on the reticle that would be exposed to the same target region to which the element would be exposed if the reticle were used for double patterning. Thus, the blank prevents target region from being exposed more than once.

Abstract: A system for connecting an interface of an electronic device between first and second fabrics includes a constraint generator that associates first and second conditions with the interface, a first equation solver that solves one or more first equation to select a first plurality of connectors in the first fabric and a second plurality of connectors in the second fabric that satisfy the first condition based on an optimality criterion for the interface; and a second equation solver that solves one or more second equation to select one of the first plurality of connectors in the fabric and one of the second plurality of connectors in the second fabric that satisfy the second condition based on the optimality criterion for the interface.

Abstract: A method, system, and computer program product are disclosed for performing RC extraction. The present approach can consider multiple types of manufacturing processes, and allows location-based prediction data to be used in the context of net-based analysis. RC extraction can be more accurately performed based upon net-specific top and bottom adjustments to thickness prediction that are location-based. The net-based prediction data can be used for other purposes as well, such as to perform electrical hotspot analysis, to visually display physical properties of the nets, or allow queries for other data analysis purposes.

Abstract: Systems and methods for modeling a multilayer integrated circuit include three-dimensional interconnect models in multilayered substrates for greater accuracy. Mesh models are used to resolve effects of nearby elements and grid models are used to resolve effects of far-away elements. Sidewall mesh elements of three-dimensional interconnects are projected onto parallel (or substantially parallel) grids between the top and bottom walls of the interconnects so that grid models can be used to resolve three-dimensional effects of interconnects in multilayered substrates.

Abstract: The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method for circuit floorplanning is provided. The method comprises generating a floorplan through a floorplanner, performing a lithography-analysis within the floorplanner on at least a portion of the floorplan, and generating one or more violations that result from the lithography-analysis. Some embodiment, in addition to viewing a floorplan, further comprise of modifying the floorplan. Furthermore, some embodiments provide a method that further comprises fixing the violations that result from the lithography analysis.

Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.

Abstract: Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC based on the designed IC layout. Some embodiments concurrently select an optimal pair of wiring and illumination configurations. Other embodiments select an illumination configuration based on the selected wiring configuration. Yet other embodiments select a wiring configuration based on the selected illumination configuration. In some embodiments, selecting the illumination configuration entails selecting at least one stepper lens for the IC layout, where the stepper lens illuminates at least one mask for at least one particular layer of the IC layout. In some embodiments, this selection entails selecting a stepper lens for each particular layer of the IC layout.

Abstract: A computerized method of characterizing a DUV includes executing in a verification environment (VE) a set of verification tests to stimulate the DUV to collect test results from the DUV. The method further includes collecting a set of failure data for the test results; and generating sets of common failures based on clusters of features of interest in the set of failure data. The method further includes generating a set of hints from the common failures; wherein the hints indicate a potential failure mode or a potential root cause failure of the DUV for the test results for the simplified set of tests; and generating a set of debug data from the clusters of features of interest. The method further includes transferring the set of hints and the set of debug data to a user computer for storage, display, and use in an interactive debug session of the DUV.

Abstract: Systems, apparatus, and methods of timing analysis with a multi-operating region gate model are disclosed, including modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation; in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation; and, in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation. Instantaneous output current provided by the time varying voltage dependent current source in the VCR region is responsive to time and the instantaneous output voltage of the logic gate. Instantaneous output current provided by the time-invariant voltage dependent current source in the AR region is responsive to the instantaneous output voltage of the logic gate.

Abstract: Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines, identifies criteria for hotspots/metrics or optimization objective function; performs the initial hotspot or metric prediction; identifies correction candidate(s); applies a correction candidate to the electronic circuit design; and determines whether the outcome of applying the correction candidate is acceptable. The method or the system identifies custom correction candidate(s) or custom command(s) and identifies one or more hints for the predicted hotspots or metrics; provides a single architecture to use a first model for hotspot identification/correction and a second model for design check; and provides the capability to apply a correction for a hotspot or metric, evaluate the effectiveness of the correction on the fly, and revert any changes made to the electronic circuit design by the correction.

Abstract: Method, system, and computer program product for saving and restarting discrete event simulations are provided. A discrete event simulation of a scenario is performed via a process executing on a system. The process includes one or more application threads. A checkpoint of the process is created at a point in time when a command to save the discrete event simulation of the scenario is received. The checkpoint includes data elements of the process and the one or more application threads of the process that are stored in components of the system at the point in time. These data elements reflect a state of the process and the one or more application threads of the process at the point in time. The checkpoint is saved to one or more files in the system that are usable to later restart the discrete event simulation of the scenario from the point in time.

Abstract: Method and apparatus for controlling power in an emulation system are described. In one example, a first interface is configured to receive requirement information for a logic module to be emulated from a host computer system. The requirement information includes at least one of a power requirement or a thermal requirement. A second interface is configured to receive measurement data from sensors in the emulation system. A controller is configured to control at least one of a synchronization system, a power regulation system, or a thermal system in the emulation system in response to the requirement information and the measurement data to reduce power load of the emulation system.

Abstract: A system, method, and computer program product is disclosed for utilizing dual-value signals, such as hierarchical dual-value signals, for mixed-signal simulation. Such dual-value signals can hold both analog and digital representations of a signal and use the appropriate representations based on which block (analog or digital) for which there is an interaction.

Abstract: Various embodiments of the present invention provide for automated synthesizing of a circuit wrapper for an integrated circuit element. Specifically, some embodiments of the invention provide computer-aided design (CAD) support for automated circuit wrapper generation, especially circuit test wrappers. Additionally, various embodiments of the invention result in optimally designed and segmented circuit wrappers that are configured for both parallel instruction mode and serial instruction mode.

Abstract: A method for modeling state-retention logic includes: specifying a circuit that includes an arrangement of circuit elements, wherein a portion of the circuit is organized into a power domain with a power-domain control for effecting power variations within the power domain, and the power domain includes a state-retention cell that includes a retention element with a retention-element control for saving state-retention-cell values in the retention element during power variations in the power domain; determining one or more pattern faults for detecting defects in state-retention operation of the circuit by associating circuit element values with values for the power-domain control or the retention-element control; and saving one or more values for the one or more pattern faults.

Abstract: Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification.

Abstract: Disclosed are improved methods, systems, and computer program products for implementing inherited connections for electronic designs. Scoped default connection or global nets are used in inherited connections for default expressions, where the default connection/global net that is applied to a particular portion of the design is scoped by being limited in its application only to certain hierarchical portions of the design.

Abstract: A method of determining a Negative Bias Temperature Instability (NBTI) effect that combines degradation and recovery for dynamic operation of an integrated circuit (IC) includes: specifying one or more parameters for a degradation model for the IC during a stressed portion of a voltage cycle; specifying one or more parameters for a recovery model for the IC during an unstressed portion of the voltage cycle; determining a degradation value for the voltage cycle from the degradation model; determining a recovery value for the voltage cycle from the recovery model; determining an NBTI value that combines the degradation value and the recovery value for the voltage cycle; and saving at least one value for the NBTI value.