Abstract: Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In this way, congestion analysis can be directly performed along diagonal boundaries for diagonal routes, without requiring association with Gcell boundaries on Manhattan routing layers.

Abstract: Described is a process for performing an improved mixed frequency-time algorithm to simulate responses of a circuit that receives a periodic sample signal and at least one information signal. The process selects a set of evenly spaced distinct time points and a set of reference time points. Each of the reference points is associated with a distinct time point, and a reference time point is a signal period away from its respective distinct time point. The process finds a first set of relationships between the values at the distinct time points and the values the reference time points. The process also finds a second set of relationships between the values at the distinct time points and the values at the reference time points. The process then combines the first and second sets of relationships to establish a system of nonlinear equations in terms of the values at the distinct time points only. By solving the system of nonlinear equations, the process finds simulated responses of the circuit in time domain.

Abstract: Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a process referred to as global constraint budgeting. An autorouter finds paths in the layout to satisfy the local constraints and ignores the global constraints. The local constraints are updated before each routing pass to ensure that routes are completed on individual direct connections while also satisfying the global constraint.

Abstract: A method and system are provided for automatically verifying terminal or bump compatibility in a stacked multi-chip architecture during integrated circuit design verification by comparing interfacing terminal layers from a first chip layout file and a second chip layout file and flagging connectivity problems or features that may give rise to problems and displaying these flagged problems or features to a user.

Abstract: According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Abstract: According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the layout-versus-schematic errors, generates a graphical representation of the layout netlist and a graphical representation of the schematic netlist, displays an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist and then, highlights the identified layout-versus-schematic errors that are present.

Abstract: A method of simulating parametric variations in an integrated circuit (IC) includes: specifying an IC model, wherein the IC model includes one or more parameters for variation about a nominal condition; calculating parametric perturbations about the nominal condition; and saving one or more values for the parametric perturbations in a computer-readable medium. Calculating the parametric perturbations includes: simulating the nominal condition for the IC; determining perturbation values for the IC model about the nominal conditions, wherein the perturbation values include linear time-varying matrices and parametric right-hand sides, determining a performance metric for the IC and a performance sampling vector for sampling the performance metric about the nominal condition from the perturbation values; and determining voltage-sensitivity values and performance-sensitivity values from the perturbation values and the performance-sampling vector.

Abstract: A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by using a computer so that one or more performance metrics can be evaluated for the circuit. In some cases, test chips may be used to determine device correlations for arrangements corresponding to different layout styles.

Abstract: Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different preferred direction than the particular wiring layer. In addition, each region has a local preferred direction that differs from the local preferred direction of at least one other region in the set. Furthermore, at least two regions have two different polygonal shapes and no region in the set encompasses another region in the set. Some embodiments also provide a Graphical User Interface (GUI) that facilitates a visual presentation of an LPD design layout and provides tools to create and manipulate LPD regions in a design layout.

Abstract: In one embodiment, a method comprises partitioning a circuit description into a plurality of simulateable partitions. The partitioning is independent of a hierarchy specified in the circuit definition. The method also comprises sorting the plurality of simulateable partitions into one or more groups, wherein each simulateable partition included in a given group is equivalent to each other partition in the given group. Further, the method comprises simulating a first simulateable partition in the given group responsive to one or more input stimuli to the first simulateable partition. For each other simulateable partition in the given group that has approximately the same input stimuli as the first simulateable partition, the method still further comprises using a result of simulating the first simulateable partition as a result of the other simulateable partition.

Abstract: An improved approach for implementing metal fill on an electrical device without causing creating cross-coupling capacitance problems is disclosed. Timing aware metal fill insertion is performed to avoid or minimize cross-capacitance problems on the IC design. A cost may be assigned to different candidate metal fill shapes. The cost is associated with the expected effect upon timing requirements by the metal fill shape, with lower costs corresponding to lower expected impacts upon the timing requirements. To meet density requirements, lower cost metal fill shapes are inserted prior to higher cost metal fill shapes.

Abstract: Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion during verification of a logic design. An evaluation engine is generated that encodes, using a non-deterministic finite automata (NFA) model, temporal behavior of the logic design required by the assertion for a single attempt to evaluate the assertion. The evaluation engine is implemented in first reconfigurable hardware. The logic design is simulated over a plurality of clock events. Attempts to evaluate the assertion by the evaluation engine are preformed sequentially based on input stimuli obtained from the logic design during simulation thereof. Each of the attempts results in one of the assertion passing, the assertion failing, or the assertion requiring further evaluation.

Abstract: Method, apparatus, and computer readable medium for simulating a logic design having power domains are described. In some examples, a switchable power domain of the power domains is identified, the switchable power domain having primary inputs and having a power state switchable between a power-on state and a power-off state. The logic design is traversed to analyze driver and load logic of each of the primary inputs to the switchable power domain to identify any pure pass-through nets each of which has no driver and no load logic in the switchable power domain.

Abstract: Method and apparatus for controlling power in an emulation system is described. In one example, power is controlled in a processor-based emulation system coupled to a host computer. A logic design is processed to identify unused resources in the emulation system during an emulation cycle. Power of the unused resources is controlled during emulation of a design under verification corresponding to the logic design by the emulation system. The resources may be identified as being unused during one or more steps of the emulation cycle. The power of the unused resources may be controlled by at least one of: powering down one or more of the unused resources; disabling one or more of the unused resources; freezing inputs to one or more of the unused resources; or setting inputs to one or more of the unused resources to a constant state. In this manner, power consumption of the emulation system is reduced.

Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method performs circuit pruning for each of distinct vectors. The circuit pruning includes identifying an active circuit for each vector. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed. The circuit pruning and circuit simulations are repeated for remaining ones of the plurality of substantially distinct vectors. The results of the circuit simulations are then stored on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors.

Abstract: An apparatus and method for optical lithography verification includes filtering a lithography simulation of proposed sub-lightwave pattern formations during at feast one design phase or manufacturing phase of an article of manufacture having sub-lightwave structures and then detecting design phase or manufacturing phase defects in response to the filtering of the lithography simulation.

Abstract: Method and apparatus for implementing a task-based interface in a logic verification system is described. In some examples, a task server and a context memory are implemented in a hardware accelerator for a task. The task server is configured for communication with the logic design. A task stub configured for execution by a computer for the task is generated. Calls to the task are received from a test bench in the computer at the task stub. Remote procedure call (RPC) channels are established in response to the calls. Values of input arguments for the calls are transferred to the context memory through the RPC channels. Execution of threads of the task in the task server is triggered using the values of the input arguments in the context memory as parametric input.

Abstract: An improved approach for locating and identifying IP for an electronic design is described. The present approach addresses the situation in which an IP catalog does not contain any IP which matches the exact requirements of an electronic design for which the IP is to be used or integrated.

Abstract: A method and apparatus for mask optimization is provided. Mask design and production is optimized by providing proper weighting parameters for critical features. The parameters may include information such as parametric information, functional information, and hot spots determination.

Abstract: A method, system, and computer program product are disclosed for automatic test generation for a compiler. In one approach, the method, system and computer program product represent a test case for the compiler in a structure with one or more elements of a programming language, associate at least one syntactic rule and semantic rule with the one or more elements in the structure, create a test with the structure compiling the test with the compiler, and display results of the test.