Abstract: Techniques are presented for improving parametric yield. As part of an automatic sizing process for a circuit, one set of techniques receives a target value for a performance goal and then optimizes, with respect to the number of standard deviations, the distance by which the mean value of a distribution of the performance goal differs from the target value. In a second set of techniques, as part of an automatic sizing process during a circuit design process, the operation of the circuit is simulated to determine the distribution of a performance goal for a first design point. It is then determined whether a second design point is sufficiently close to the first design point and, if so, the simulation for the first design point is used for evaluating the second design point in an optimization process.

Abstract: A system and method for securely and automatically moving a resource, such as a server, between secure network environments include a secure auto-migration control program. The secure auto-migration program may automatically reconfigure a computing resource used in a first secure network environment to be used in a second secure network environment and logically move the computer resource from the first secure network environment to the second secure network environment.

Abstract: Techniques that can improve the efficiency of routing where connections are subject to elongation constraints. The design can be optimized by estimating elongation needed to meet constraints after an initial routing solution has been generated, but before elongation is actually applied to detailed paths. Paths can be re-routed at this earlier stage if it is determined that too much elongation, or too much elongation in crowded areas, will need to be added after the detail routing stage.

Abstract: A method for detecting program code errors including searching for lines of command codes in the program code. A line of command code includes command codes and indices. The lines of command codes are organized as paragraphs. At least one of the lines of commands codes in each paragraph is different from the other lines of commands codes in the paragraph. The method further including separating the command codes from the indices for the lines of command codes, wherein the indices are a matrix of indices, and each row of indices in the matrix of indices includes the sets of indices for each of the lines of command codes from one of the paragraphs; determining each set of vertical indices in the matrix of indices that does not match a known series; and reporting to a user computer each set of vertical indices that does not match the known series.

Abstract: A method of specifying system level constraints for connecting an interface of an electronic device between first and second fabrics includes specifying one or more first condition relating to a placement of the interface, specifying one or more second condition relating to a connection of a net in the interface between the first and second fabrics, generating one or more first equation expressing the first condition as a function of the location of the connectors, generating one or more second equation expressing the second condition as a function of the location of connectors, generating one or more third equation expressing an optimality criterion for the interface, and outputting the one or more first equation, the one or more second equation and the one or more third equation to a data file in a computer readable format.

Abstract: A method for identifying an anomaly in an electronic system includes receiving, from a computer-readable storage medium, a plurality of entries from a successful simulation test of the electronic system, each of the plurality of entries including information about simulation time. The method also includes, with one or more computer processors, determining time sequence relationship between pairs of entries selected from the plurality of entries and identifying allowable sequences of entries using information related to the first plurality of entries and the time sequence relationship. The method includes receiving a second plurality of entries from a failed simulation test of the electronic system, each of the second plurality of entries including information about simulation time. The method includes analyzing the second plurality of entries and identifying one or more anomalies in the electronic system based on the analysis of the failed simulation test.

Abstract: A method for automatically generating and prioritizing several design solutions that resolve a double patterning (DP) loop violation in an IC design layout. The method of some embodiments receives a DP loop violation marker and identifies pairs of edges of shapes that form a double patterning loop based on the DP loop violation marker. For each pair of edges that violates the design rule, the method generates one or more design solutions. Each design solution moves a single edge or both edges to resolve the violation. The method of some embodiments computes the cost of applying each design solution to the IC design layout and prioritizes the generated solutions for all the identified pairs of edges based on the computed cost for each solution. The method in some embodiments then selects a solution from the prioritized solutions and applies the selected solution to the design layout.

Abstract: A method and system for providing multi-process protection using direct memory mapped control registers is disclosed. According to one embodiment, a computer-implemented method provides a set of control registers for each execution unit of a plurality of execution units in a controller switch. The controller switch facilitates communication between a host system and one or more devices connected to a plurality of device ports of the controller switch. A device driver is provided to allow users' processes to access the controller switch and to grant exclusive access to each execution unit of the plurality of execution units. A first access request to access an execution unit of the plurality of execution units is received from a first process. A set of direct accessible addresses to the set of control registers of the execution unit is allocated, and the first process is granted to exclusive access the execution unit until the first process release the exclusive access to the execution unit.

Abstract: A method and system for reducing switching activity of a spreader network during a scan-load operation is disclosed. According to one embodiment, a spreader network receives a plurality of scan input signals from a tester. A linear feedback shift register of the spread network is updated using the plurality of scan input signals. Each bit of the linear feedback shift register is shifted at each shift cycle for a plurality of shift cycles. The linear feedback shift register outputs a nonlinear gating signal using a first set of outputs and a data value feeding one or more scan chains of the spreader network using a second set of outputs. The pipeline clock of a pipeline element of the scan chains is gated using the nonlinear gating signal, and the data value is fed to the scan chains based on the pipeline clock. The scan chains are fed with updated values at the pipeline stage.

Abstract: A hardware emulator having an emulation unit with a shadow processor is described. The shadow processor is capable of performing an extra look up table (LUT) operation in addition to the LUT operation performed by a processor within the emulation unit. The emulation unit comprises a memory for supplying a first amount of data to a shadow processor register, wherein the shadow processor register stores the first amount of data for later retrieval. The data stored in the shadow processor register function as operands for a truth table stored in the memory and are used to select a function bit out from the memory. The selected function bit out represents a Boolean evaluation of the operands.

Abstract: A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful routing of all needed terminals, an at least partially routed circuit design may be output.

Abstract: A method for integrated circuit design is disclosed including determining if at least one dynamic class and at least one virtual function are present within a chip program description of an integrated circuit design; and if so then converting the at least one virtual function into a non-virtual function, generating at least one virtual pointer for the at least one dynamic class, converting at least one function calling the at least one virtual function into at least one conditional function responsive to a value of the at least one virtual pointer, and generating dataflow graphs of the at least one dynamic class and the at least one conditional function that can be transformed into a synthesizable design description of the integrated circuit design.

Abstract: A method and system are provided for parametrically adapting a behavioral model pre-configured for a preset supply reference level to fluctuations therein. The behavioral model is adaptively scaled for deviation of the electronic system supply reference from its preset level. The scaling includes reconstructing a surrogate device parametrically representative of a portion of the behavioral model's undisclosed circuit. The reconstruction includes pre-setting a transistor type for the surrogate device, such that the surrogate device is configured with a conductive channel current-voltage characteristic of the preselected transistor type. Device-specific properties for the surrogate device are generated based on selective cross-correlation of operating points between the conductive channel current-voltage characteristic and V-t and I-V curves associated with the behavioral model.

Abstract: Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further partitioned into sub-containers to more efficiently provide space pruning during query operations. According to one approach, structures maintained to track existence of objects in a descendent hierarchy.

Abstract: The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of “events” which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.

Abstract: A method and an apparatus are described for allowing several different applications to incrementally collaborate while making changes to a circuit design.

Abstract: For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.

Abstract: The present disclosure relates to a computer-implemented method for automatically generating a power management verification component. The method may include receiving one or more inputs including a power intent definition. The method may further include automatically generating a power management verification environment based upon, at least in part, the power intent definition, the power management verification environment including at least one of a driver and a monitor.

Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

Abstract: An adaptive mesh of virtual nodes is provided to analyze the performance of a power/ground plane pair having an irregular shape. Plane transmission line characteristics and regional modal resonances can be modeled accurately, and with a significant decrease in simulation time as compared to traditional methods. A variable-sized cell structure is constructed with smaller cells in irregular regions and with larger cells in uniform regions. Grid nodes may thus stay aligned along length and width to allow parameters of equivalent circuit models to be scaled appropriate to the cell size.