Abstract: A method is provided for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements or performs a set of two or more functions. Some embodiments provide a method for producing a circuit description of a design that (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the replacement sub-network in certain conditions. Some embodiments provide a data storage structure that stores a plurality of sub-networks based on parameters derived from the output functions of the sub-networks.

Abstract: Some embodiments provide a hierarchical routing method that uses diagonal routes. This method routes a net within a particular region of an integrated circuit (“IC”) layout. This net includes several pins in the region. The method initially partitions the particular IC region into a first set of sub-regions. It then identifies a first route that connects a group of first-set sub-regions that contain the net's pins. The identified first route has an edge that is at least partially diagonal. The method next partitions the first-set sub-regions into a second set of smaller sub-regions. It then propagates the first route into the second-set sub-regions.

Abstract: Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ration of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.

Abstract: A method for generating a test vector for functional verification of circuits includes providing a representation of a circuit, where the representation includes a control logic component and a datapath logic component. The method also includes reading one or more vector generation targets, and performing word-level ATPG justification on the control logic component to obtain a control logic solution. The method further includes extracting one or more arithmetic functions for the datapath logic component based on the control logic solution, and solving the one or more arithmetic functions using a modular constraint solver. The modular constraint solver is based on a modular number system.

Abstract: Some embodiments of the invention provide a method for identifying a path in a design layout. Based on the design layout, the method defines a triangulated graph that has sets of source and target states and two orthogonal axes. The method specifies at least one path that starts from one state. It then iteratively specifies new paths by expanding previously specified paths in the graph until identifying a path that connects the source and target states. At least one of the expansions of a previously specified path is an expansion to a line that is not aligned with the axes of the graph.

Abstract: In system design simulators, probes are software objects that collect data from simulated system components. A probe synchronization method and device are used to collect simulation data from the components during a period of interest. For example, a given event that occurs during the simulation may signal the beginning of the period, and another event may signal the end of the period. An acquisition window having a starting point and an ending point coinciding with the occurrence of the events may be used by a probe master to cause one or more probes to collect data during this period of interest. A unique Identifier or Tag of this period of interest is generated by the Probe Master and sent to all the slave probes. This Tag is dumped in the simulation database. It allows post-processing correlations between high-level simulation events and low-level model reactions.

Abstract: A method and system for evaluating performance level models of electronic systems having both hardware and software components is provided. The system and method allow for the simplified implementation and testing of several different architectural designs for compliance with the desired operational requirement of a designed electronic system.

Abstract: Some embodiments of the invention provide a method for identifying a path between a set of source states and a set of target states in a space with more than two dimensions. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. At least some of the states are non-zero dimensional states. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method specifies at least one path that starts from one state. It then iteratively specifies new paths by expanding previously specified paths to other states in the space until identifying a path that connects the source and target states. At least one of the expansions of a previously specified path includes an expansion in more than two dimensions of the space.

Abstract: One embodiment of the invention is a method of identifying a set of paths between a set of source routable elements of a net and a set of target routable elements of the net. The set of paths has to have a minimum acceptable number of paths. The method specifies a first total cost. It then performs a first depth-first search to identify the set of paths, where each path has a cost that does not exceed the first total cost, and each path includes a set of expansions from the set of routable-element sources to the set of routable-element targets. If the search cannot find the acceptable number of paths, it increments the total cost and performs a second depth-first search to identify the set of paths, where each path has a cost that does not exceed the incremented total cost.

Abstract: The disclosure presents a formulation to support simulatable subset (also known as ‘simple-subset’) of a property specification language. This method is applicable for model checking and simulation. In this formulation, the ‘simple-subset’ is transformed to a set of basic formulas. Verification engines are required to support the basic formula only. The basic formula is a form of automata in the property specification language. This is called SERE implication. The efficiency of verification is dependent on size of automata. Miscellaneous opportunistic rules are applied to optimize SERE implication formulas.

Abstract: Some embodiments of the invention provide novel methods for removing acute angles form routes in a design layout. The method reacts a route with several segments. It then identifies an acute angle between first and second contiguous segments of the route. The method next inserts a third segment between the first and second segments, where the third segment has an associated shape that fills the acute angle between the first and second segments.

Abstract: Some embodiments of the invention provide a method of specifying a cost function that represents the estimated distance between an external state and a set of states in a multi-state space that represents a region of a design layout. The method identifies a first polygon that encloses the set of states. It then identifies vectors to project from the vertices of the first polygon. Based on the projected vectors, the method specifies a first cost function. The method also identifies a second polygon that encloses the set of states. It also identifies vectors to project from the vertices of the second polygon. Based on the projected vectors, the method specifies a second cost function. The method then derives a third cost function from the specified cost functions.

Abstract: In a method of automatically sizing and biasing a circuit, a database is provided including a plurality of records related to cells that can be utilized to form an integrated circuit. A cell parameter of a cell for a circuit is selected and compared to cell parameters residing in the records stored in the database. One record in the database is selected based upon this comparison and a performance characteristic of the circuit is determined from this record.

Abstract: Some embodiments provide an analytical placement method that considers diagonal wiring. This method formulates an objective function that accounts for the use of diagonal wiring during routing. Some embodiments use horizontal, vertical, and ±45° diagonal lines.

Abstract: An assertion based transaction recording method is used to represent a signal-level transaction having a prefix and a suffix as an abstract transaction. The method models the signal-level transaction as an assertion requiring that the transaction suffix must occur following any occurrence of the transaction prefix. A finite-state-machine (FSM) implementation of the assertion records a tentative abstract transaction upon recognizing the first condition of the prefix. If the FSM recognizes that the prefix cannot complete, it cancels, or deletes, the tentative abstract transaction record. The implementation can track multiple tentative abstract transaction records that may co-exist prior to completion of the transaction prefix. Upon recognizing that the transaction prefix corresponding to the start point of the tentative abstract transaction has completed, the tentative abstract transaction record is committed.

Abstract: Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the delay cost of a placement configuration by accounting for the potential use of diagonal wiring in the layout. Some of these embodiments derive the delay cost from an estimate of the wirelength needed to route the nets in the region.

Abstract: System and method for converting a flat netlist into a hierarchical netlist are disclosed. The method includes receiving the flat netlist, traversing the flat netlist in a bottom-up fashion, and identifying isomorphic subcircuits in the flat netlist. The method further includes creating a set of cross-coupling capacitor collections for storing information of cross-coupling capacitors, creating a set of net collections for storing information of isomorphic subcircuits, traversing each hierarchical level of the hierarchical netlist in a top-down fashion, and generating the hierarchical netlist using the set of net collections and the set of cross-coupling capacitor collections.

Abstract: Method and system for determining electrical isomorphism between two electrical networks are disclosed. In one embodiment, the method includes representing the circuit as a hierarchically-arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically-arranged set of branches including a first branch that includes a first electrical network and a second branch that includes a second electrical network, where the first and second branches are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches. Next, the method determines whether the first and second electrical networks are electrically isomorphic networks. If the first and second electrical networks are determined to be electrically isomorphic networks, the first and second electrical networks are represented with a single electrically isomorphic network.

Abstract: An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide an IC package routing solution. The global topological solution is used in conjunction with necessary design parameters to determine the optimal geometric routing solution which can include reassignment of IC nets and/or pin assignments and/or relocation of IC nets.

Abstract: A clock tree synthesis (CTS) tool determines how to position a hierarchy of buffers for fanning out a clock signal to clocked devices (“sinks”) within an integrated circuit (IC). The tool first clusterizes the sinks and places a lowest level fan-out buffer near each cluster. The tool then iteratively places progressively higher level buffers by clusterizing a last-placed buffer level and then placing a next higher level buffer near the centroid of each lower level buffer cluster, until the tool has placed buffers at a mid-level for which variation in path distances between that level and a next higher buffer level exceeds a predetermined limit. The CTS tool then places a top level buffer at the centroid of the mid-level buffers, divides the layout into partitions, each containing a similar number of mid-level buffers, and then places a second-highest level buffer in each partition.