Abstract: Views for signals and instances are provided in a table based design entry system. The signal view allows a designer to enter signals to be used in a design. The signals may be individually entered or imported from pre-defined or external packages of signals. The instance view allows the designer to enter components and to define connectivity of pins of the components to signals. The components may be entered individually or imported from predefined or external packages. An naming routines provides signal name generation and copying names of other components (e.g., pin names) to name the signals. Data entered into the table based entry system is checked for errors (duplicate names, syntax, etc.), and exported to other design tools for processes such as simulation, layout, etc.

Abstract: According to one aspect, a work request that specifies first and second jobs is received. The first job comprises a first task and the second job comprises a second task. The work request is processed to automatically determine whether the jobs have any dependencies that have not been satisfied. In response to a determination that the jobs have no dependencies that have not been satisfied, the jobs are caused to be executed in parallel. As a default manner of operation, the tasks included in each respective job are collectively executed in parallel, whereas tasks within a given job are not executed in parallel. In an embodiment, the tasks are executed on one or more servers of a group of networked servers.

Abstract: Some embodiments of the invention provide a method for processing a hierarchical data structure that includes a parent data set and first and second child data sets of the parent data set. The parent and first and second child data sets includes several data tuples. From the second child data set, the method identifies a first data tuple that is not in the first child data set and that is relevant for the processing of the data tuples within the first child data set. The method then assigns the first data tuple to the first child data set and then processes the first child data set based on the data tuples included in the first child data set and assigned to the first child data set. In some embodiments, the method also identifies, from the parent data set, a second data tuple that is not in the first child data set and that is relevant for the processing of the data tuples within the first child data set.

Abstract: In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a “master module” and the others designated “clone modules”. A placement and routing (P&R) tool initially places all of the cell instances of the clone modules at the center of their reserved areas. The P&R tool then employs a conventional placement algorithm to iteratively adjust positions of cell instances of all other modules, including the master module within their reserved areas in a manner that tries to minimize net lengths. The P&R tool copies the placement within the master module area into the clone module areas either after every N>0 iterations of the placement algorithm and/or after the placement algorithm has completed placement for the master module area.

Abstract: A method for routing of some embodiments defines global routes for nets in an arbitrary region of a circuit layout in which each net has a set of pins. The method uses a first set of lines of measure the length of the global routes, a second set of lines to measure congestion of the global routes, and a third set of lines to partition the arbitrary region into a first set of sub-regions. For each net, the method identifies a global route that connects a group of first-set sub-regions that contain the net's set of pins.

Abstract: Some embodiments of the invention provide a method of pre-computing routes for nets a region of a design layout. These routes are used by a router that uses a set of partitioning lines to partition the region into a plurality of sub-regions. For each particular set of potential sub-regions, the method initially identifies a set of routes that traverse the particular set of potential sub-regions. For each particular route identified for each particular set of sub-regions, the method then determines whether the particular route is stored in a storage structure. If not, the method stores the particular route in the storage structure.

Abstract: An environment is described in which multiple companies can securely collaborate on a design or other project. The environment includes a set of resources residing on a set of one or more utility servers maintained by a first company, an access control mechanism for controlling access to the set of resources, a secure network connection between the set of utility servers and a second company, and a remote controller for remotely viewing, by an authorized individual from the second company, a user interface of an application while an authorized individual from the first company is executing the application on the set of utility servers. The secure network connection includes a secure association mechanism for establishing a secure association between participating parties, a virtual point-to-point network connection for transmitting data between associated parties, and an encryption/decryption mechanism.

Abstract: The present invention introduces a method for implementing a gridless non Manhattan router by modifying an existing gridless Manhattan router. In the method of the present invention, a tile based router that uses tiles to represent circuit geometry or free space between circuit geometry is first selected. Next, at least one tile routing layer of the tile based router is rotated to implement a diagonal wiring layer. The code of the router is then adjusted to ensure that a via that will connect a Manhattan layer to a non Manhattan layer (a diagonal layer) will fit within a tile on both layers.

Abstract: Concurrent engineering among multiple design groups is facilitated by maintaining design changes in a data model of a design being developed. Design changes for each group are made from a baseline design. Changes are tracked by maintaining change information from all but an owner of the original baseline design. Changes are synchronized by identifying owner and non-owner changes and merging the changes to produce a final design. Since non-owner changes are tracked, the baseline design is not needed in synchronization. Preferably the invention is applied to electronic designs made by multiple design groups at geographically diverse locations. The invention may also be applied to any system where configuration management of developed software, parts, or any design is needed.

Abstract: A method for inferring a requested data input function of a sequential cell from a library of candidate cells, wherein the requested cell and the candidate cell are expressed as polynoms and then divided. The method generates polynomial expressions of the inhibition, transformation and inference steps necessary to convert the candidate cell into the requested cell. The use of polynomial expression and division greatly reduces the number of rules necessary to accommodate the varying combinations of requested cell and candidate cell functions.

Abstract: A machine-implemented, simulations-supporting system creates a hierarchy of data structures for simplifying the task of identifying iso-topological, and iso-geometric, and iso-static instances of subcircuit-definitions. The behaviors of such isomorphic and iso-static instances can be simultaneously predicted by appointing a simulation leader for them and using the simulation leader in combination with a respective simulation model to predict the behavior of the simulation leader. The predicted behavior of the leader is then copied for the followers. In one embodiment, state-describing S-circuit cards each point to a respective, and possibly merged, I-circuit card. The I-circuit cards each point to respective, and possibly merged, element instantiating cards (AG-cards) as well as to respective, and possibly merged, interconnect-topology describing cards (T-circuits).

Abstract: Some embodiments provide a method of pre-computing routes for nets in a region of an integrated circuit (“IC”) layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. For a particular set of potential sub-regions, the method then identifies a set of routes that traverse the particular set of potential sub-regions, where at least one of the identified routes has at least one diagonal edge. The method then stores the identified routes.

Abstract: In an automated integrated circuit design, if the performances of a layout of circuit devices are not within predetermined tolerances of performance specifications, at least one of the circuit devices is resized or repositioned and an updated value of a device parameter for each resized or repositioned circuit device is determined. A difference between the initial and updated value of each device parameter is then determined and each difference is combined with a ratio formed from changes in the value of one of the device parameters and changes in the value of one of the performances affected by the device parameter. The result of this combination is then combined with the initial value of the performance to determine an updated value therefor.

Abstract: A method for modeling a mixed-language and mixed-signal (MLMS) design is disclosed. The method includes receiving an MLMS design comprising at least a digital driver, a digital receiver, and an analog block connected by an MLMS net in a hierarchical structure and identifying analog-digital boundaries of the MLMS design. For each analog-digital boundary, the method further includes a) selecting a connect module (CM) by using a predetermined discipline resolution procedure; b) determining input driving values of the CM; and c) connecting the digital driver, the digital receiver, and the analog block to the CM. The method repeats steps a), b), and c) on all analog-digital boundaries of the MLMS design.

Abstract: When an IC layout is to include time-constrained signal paths, a placement plan defining positions of cells forming the IC is analyzed to estimate lengths of nets needed to interconnect the cells based on the positions of cells included in those signal paths. A capacitance and resistance of each net is then estimated based on its estimated length. The delay through each time-constrained signal path is then estimated based on the estimated capacitance and resistance of each net to be included in the time-constrained signal path and on the terminal impedances, switching speeds and driving strengths of the cells included in the signal path. The estimated path delay for each signal path is then compared to its timing constraint to determine whether that signal path is a “critical signal path” likely to fail to meet its timing constraint following development of a detailed routing plan.

Abstract: A method for modeling a circuit design includes synthesizing the circuit design to create a first gate-level representation of the circuit design. The method also includes analyzing a second gate-level representation of the circuit design to learn architecture information, and resynthesizing the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design. A computer-readable storage medium has stored thereon computer instructions that, when executed by a computer, cause the computer to synthesize a circuit design to create a first gate-level representation of the circuit design.

Abstract: A system and method for enabling Intellectual Property (IP) Blocks to be reused at a system level. The present invention represents the IP blocks as blocks that exchange messages without needing to represent the functionality of the IP blocks. The implementations of these IP blocks exchanges messages through complex signaling protocols. In conventional systems, interfacing between IP blocks that use different signaling protocols is a tedious and error prone design task. The present invention uses regular expression based protocol descriptions to show how to map the message onto a signaling protocol. Given two protocols, the present invention builds an interface machine that automatically labels data referenced by all protocols. The present invention is capable of generating the interface even when the data sequencing of the two protocols differs.

Abstract: A method is provided for compiling a model for use in a simulation, the method comprising receiving a description of the model; and automatically converting the description into an implementation of the model that is customized for a selected analysis during simulation.

Abstract: Disclosed is a method, system, and computer program product for performing interblock stitching for electronic designs. According to some approaches, interblock stitching is accomplished by implementing a stitching region between the block and external routing structures. The stitching region is implemented using local preferred direction approaches.

Abstract: A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path independent of the solution paths for all other nets. The electrical and physical constraints of the system are initially ignored or greatly relaxed. Over each design iteration, the constraints are tightened until a complete, global, topological solution is found. Once a topological solution is found, it is converted into a geometric solution. In the event that no geometric solution exists for that topological solution, then the iteration process is resumed taking into consideration this additional information. The result is the ability to quickly autoroute highly-constrained PCB designs with minimal operator input.