Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of crosstalk cancellation circuitry for a receiver (e.g. an AC coupled DDR5 receiver). One embodiment is a receiver apparatus with crosstalk victim and aggressors lines. The cancellation circuitry involves an amplifier and buffering circuitry to provide inductive and capacitive crosstalk cancellation voltages. Some embodiments can additionally involve circuitry for autozeroing modes for AC coupled receiver lines.

Abstract: Aspects of the present disclosure address improved systems and methods for core-route-based clock tree wirelength reduction. A method may include accessing an integrated circuit design comprising a clock tree comprising routes that interconnect terminals of a plurality of clock tree instances. The method further includes identifying a core route in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and the core route and determining a second offset based on a distance from the second terminal to the core route. The method further includes determining a target offset based on a combination of the first and second offsets and moving the clock tree instance toward the core route by the target offset.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. The method may include receiving, using at least one processor, an electronic design and analyzing the electronic design. The method may further include generating one or more preconditions representative of metastability effects at the output of at least one synchronizer associated with the electronic design. The method may also include generating, based upon, at least in part, the one or more preconditions, one or more properties configured to analyze a propagation of the metastability effects associated with the at least one synchronizer.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include providing, using a processor, an electronic design and determining one or more design violations based upon, at least in part, a structural observability filter. Embodiments may also include generating a violation trace based upon, at least in part, the one or more design violations and displaying the violation trace at a graphical user interface configured to allow a user to debug the one or more design violations. Embodiments may further include allowing the user to select at least one path to be waived at the graphical user interface and generating a new violation trace without the at least one path to be waived.

Abstract: Various embodiments provide for caching of error checking data for memory having inline storage configurations for primary data and error checking data for the primary data. In particular, various embodiments described herein provide for error checking data caching and cancellation of error checking data read commands for memory having inline storage configurations for primary data and associated error checking data. Additionally, various embodiments described herein provide for combining/canceling of error checking data write commands for memory having inline storage configurations for primary data and associated error checking data.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify a specification of an electronic design, a parameter for optimization, at least one optimization target for the parameter, and initial grids for the electronic design. An optimization map may be determined, by at one or more optimization modules that are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system, for the electronic design at least by performing one or more analyses that refine the initial grids for the optimization map with respect to the parameter and the at least one optimization target. The electronic design may be implemented based at least in part upon the optimization map.

Abstract: Methods and computer-readable media for testing integrated circuit designs implement a physically efficient scan by optimally balancing and connecting scan segments in a 2-dimensional compression chain architecture. A compression architecture that provides an optimal and balanced configuration of scan segments in 2D compression grids to not only decrease test time, but also to maximize compression efficiency and limit wiring congestion for IC designs that contain complex scan segments facilitates efficient scanning of data by bisecting the elements into balanced partitions of the same target scan length. A segment padding algorithm, followed by a bisecting algorithm and ultimately an element swapping algorithm may be applied to optimally balance and connect scan segments in 2-D compression chains, optimizing an efficient compression architecture which minimizes scan testing resources and time.

Abstract: The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a two stage routing analysis, wherein a first stage analysis is an intra-row routing analysis and a second stage is an inter-row routing analysis. Embodiments may also include generating an optimized routing of the one or more nets and displaying the optimized routing at a graphical user interface.

Abstract: A test circuit includes a plurality of codec logic elements arranged in a plurality of annular rings on an integrated circuit, each codec logic element configured to provide test bits to one or more respective scan chain and receive test result bits from the one or more respective scan chain. The test circuit further includes a decompressor logic arranged along at least one annular ring of the plurality of annular rings on the integrated circuit, the decompressor logic configured to provide test bits to at least one codec logic element in each annular ring. The test circuit also includes a compressor logic arranged transversely with respect to the plurality of annular rings on the integrated circuit, the compressor logic configured to receive test result bits from at least one of the plurality of codec logic elements.

Abstract: Aspects of the present disclosure address improved systems and methods for generating a clock tree based on route-driven placement of fan-out clock drivers. Consistent with some embodiments, a method may include constructing a spanning tree comprising one or more paths that interconnect a set of clock sinks of a clock net of an integrated circuit device design. The method further includes calculating a center of the set of the clock sinks based on clock sink locations in the integrated circuit device design and identifying a point on the spanning tree nearest to the center of the set of clock sinks. The method further includes generating a clock tree by placing a clock driver at the point on the spanning tree that is nearest to the center of the set of clock sinks.

Abstract: Aspects of the present disclosure address systems and methods for shortening clock tree wirelength based on target offsets in connected routes. A method may include accessing a clock tree comprising routes that interconnect a plurality of pins. Each pin corresponds to a terminal of a clock tree instance. The method further includes identifying a first and second terminal of a clock tree instance in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and a branch in a first route connected to the first terminal and determining a second offset based on a distance between the second terminal and a branch in a second route connected to the second terminal. The method further includes moving the clock tree instance from a first location to a second location based on a target offset determined by comparing the first and second offsets.

Abstract: Systems, methods, media, and other such embodiments described herein relate to insertion of test points in circuit design and associated test coverage for a circuit design. One embodiment involves a circuit design with a plurality of circuit elements and a plurality of clock gating logic elements. A first node coupled to a first circuit element is selected for insertion of a test point circuit element. Elements of the design are identified that contribute to a data state of the first node, and clock elements for these identified design elements are traced. An ungated clock input node from this trace is selected, and the clock input from this node is connected to the test point circuit element. The circuit design is then updated with this connection. In various embodiments when multiple ungated clock input nodes are identified by the trace, additional criteria are used to select among the ungated clock input nodes.

Abstract: A method for automatically finding a verification test of a plurality of verification tests that were executed in a verification process of a design under test (DUT) that satisfies a criterion, may include using a processor, obtaining from a user a criterion that relates to one or more test actions; using a processor, obtaining a log with logged execution data that includes start and end times for each action of each of the tests of the plurality of verification tests during an execution run of that test; and for each test of the plurality of verification tests, using a processor, determining from the logged data whether that test satisfies the obtained criterion, and if a test of the plurality of verification tests was determined to satisfy the obtained criterion, using a processor, executing that test on the DUT.

Abstract: The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design at a debugging platform without performing a model extraction phase and mapping one or more extracted timing models (“ETM”) to one or more netlist objects associated with the electronic design. Embodiments may further include receiving, at the debugging platform, at least one timing arc specified by a source pin and a sink pin, wherein the at least one timing arc is associated with the electronic design. Embodiments may also include generating a worst timing path based upon, at least in part, the received at least one timing arc. Embodiments may further include generating characterization information for the at least one timing arc based upon, at least in part, one or more user-specified boundary conditions.

Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems, and using information about instances that have been included in the design. In particular, the present embodiments allow for the automatic creation of WSPs by examining heights and placement orientations of instances, along with the width, spacing, and colors of instance pins and blockages. In these and other embodiments, techniques are provided for filling gaps between generated tracks, as well as for generating tracks to account for the possibility of flipped or mirrored instances.

Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.

Abstract: A system and method are provided for memory control, having selectively distributed power-on processing. A memory controller executes responsive to a master control operation to actuate a plurality of operational tasks on a memory device. The memory controller includes a first power-on block executable to actuate one or both of initialization and training operations corresponding to the memory device. A PHY portion coupled to the memory controller portion executes to adaptively configure control, address, and data signals for physically compatible passage between the controller portion and memory device. The PHY portion includes a second power-on block executable to actuate one or both of an initialization operation and a training operation corresponding to the memory device. The PHY portion is configured according to the initialization and training operations, wherein each of the initialization and training operations are selectively actuated responsive to one of the power-on blocks.

Abstract: Various embodiments provide for circuit design routing using a track assignment based on a plurality of panels (also referred to herein as a multi-panel track assignment). According to some embodiments, a track assignment of a wire within a particular panel is performed based on a primary panel bound or limit and a secondary panel bound or limit. For instance, during a track assignment for a particular wire falling within a particular panel, an embodiment can first attempt to assign the particular wire to a track that falls within panels within the primary panel bound and, if deemed not possible (e.g., due to a DRC, violation or congestion issue), the embodiment can then assign the particular wire to a track that falls within panels within the secondary panel bound.

Abstract: Systems and methods disclosed herein provide for efficiently testing memories during mission mode self-test (“MMST”) without destroying any original functional data. Embodiments provide for a converter to feed a manipulated version of the original functional data back into the tested memories. Embodiments further provide an accumulator to count the occurrences of correctable and uncorrectable errors associated with the tested memories.