Abstract: Probe head assemblies, components of probe head assemblies, test systems including the probe head assemblies and/or components thereof, and methods of operating the same. The probe head assemblies are configured to convey a plurality of test signals to and/or from a device under test and include a space transformer, a contacting assembly, and a riser that spatially separates the space transformer from the contacting assembly and conveys the plurality of test signals between the space transformer and the contacting assembly. The contacting assembly may include a frame that defines an aperture and has a coefficient of thermal expansion that is within a threshold difference of that of the device under test, a flexible dielectric body that is attached to the frame, maintained in tension by the frame, and extends across the aperture, and a plurality of conductive probes. The plurality of conductive probes may include a dual-faceted probe tip.

Abstract: Wafer-handling end effectors and semiconductor manufacturing devices that include and/or are utilized with wafer-handling end effectors are disclosed herein. The end effectors include an end effector body and a plurality of wafer-contacting surfaces that is supported by the end effector body and configured to form an at least partially face-to-face contact with a wafer. The end effectors further include a vacuum distribution manifold that extends between a robot-proximal end of the end effector body and the plurality of wafer-contacting surfaces. The end effectors also include a plurality of vacuum openings that is defined within the plurality of wafer-contacting surfaces and extends between the plurality of wafer-contacting surfaces and the vacuum distribution manifold. The end effectors further include a plurality of sealing structures each of which is associated with a respective one of the plurality of wafer-contacting surfaces.

Abstract: A prober for testing devices in a repeat structure on a substrate is provided with a probe holder plate, probe holders mounted on the plate, and a test probe associated with each holder. Each test probe is displaceable via a manipulator connected to a probe holder, and a substrate carrier fixedly supports the substrate. Testing of devices, which are situated in a repeat structure on a substrate, in sequence without a substrate movement and avoiding individual manipulation of the test probes in relation to the contact islands on the devices, is achieved in that the probe holders are fastened on a shared probe holder plate and the probe holder plate is moved in relation to the test substrate.

Abstract: Resilient electrical interposers that may be utilized to form a plurality of electrical connections between a first device and a second device, as well as systems that may utilize the resilient electrical interposers and methods of use and/or fabrication thereof. The resilient electrical interposers may include a resilient dielectric body with a plurality of electrical conduits contained therein. The plurality of electrical conduits may be configured to provide a plurality of electrical connections between a first surface of the electrical interposer and/or the resilient dielectric body and a second, opposed, surface of the electrical interposer and/or the resilient dielectric body. The systems and methods disclosed herein may provide for improved vertical compliance, improved contact force control, and/or improved dimensional stability of the resilient electrical interposers.

Abstract: Probes with fiducial marks, probe systems including the same, and associated methods. The probes include a beam portion and a probe tip that is configured to contact a device under test (DUT), and further include a fiducial mark formed on the beam portion that is configured to facilitate alignment of the probe and the DUT. The fiducial mark is configured to be visible to an optical assembly, and is in focus to the optical assembly within a depth of field of the optical assembly that is smaller than a depth of field over which the beam portion is in focus to the optical assembly. The methods include methods of utilizing and/or manufacturing the probes.

Abstract: Shielded probe systems are disclosed herein. The shielded probe systems are configured to test a device under test (DUT) and include an enclosure that defines an enclosure volume, a translation stage with a stage surface, a substrate-supporting stack extending from the stage surface, an electrically conductive shielding structure, an isolation structure, and a thermal shielding structure. The substrate-supporting stack includes an electrically conductive support surface and a temperature-controlled chuck. The electrically conductive shielding structure defines a shielded volume. The isolation structure electrically isolates the electrically conductive shielding structure from the enclosure and from the translation stage. The thermal shielding structure extends within the enclosure volume and at least partially between the enclosure and the substrate-supporting stack.

Abstract: A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under test. An upper insulating layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper conductive layer, and a lower surface. A middle conductive layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper insulating layer, and a lower surface.

Abstract: A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under test. An upper insulating layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper conductive layer, and a lower surface. A middle conductive layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper insulating layer, and a lower surface.

Abstract: Systems and methods for testing a device under test (DUT) that includes a low power output driver. The methods include providing an input signal to the DUT. The low power output driver is configured to generate a data signal responsive to receipt of the input signal by the DUT and provide the data signal to a signal analyzer via a data signal transmission line. The methods further include determining an expected data signal to be received from the low power output driver and charging at least a portion of the data signal transmission line with a co-drive output signal that is based, at least in part, on the expected data signal. The methods further include receiving a composite data signal with the signal analyzer. The systems include probe heads with a plurality of data signal transmission lines and a plurality of co-drive conductors.

Abstract: Focusing optical systems and methods for testing semiconductors are disclosed herein. The methods include receiving an image of a probe through a single optical path of a microscope, substantially focusing the microscope on the probe, and determining a vertical height adjustment between the probe and a device under test based upon the focusing.

Abstract: The contacts of a probing apparatus are elastically supported on a replaceable coupon and electrically interconnected with conductors on a membrane or a space transformer.

Abstract: In a method and a device for testing a test substrate under defined thermal conditions, a substrate that is to be tested is held by a temperature-controllable chuck and is set to a defined temperature; the test substrate is positioned relative to test probes by at least one positioning device; and the test probes make contact with the test substrate for testing purposes. At least one component of the positioning device that is present in the vicinity of the temperature-controlled test substrate is set to a temperature that is independent of the temperature of the test substrate by a temperature-controlling device, and this temperature is held constant.

Abstract: Disclosed systems and methods for testing a device under test (DUT) with a probe system are selected to test a DUT at a temperature below the dew point of the ambient environment surrounding the probe system. Probe systems include a measurement chamber configured to isolate a cool, dry testing environment and a measurement chamber door configured to selectively isolate the internal volume of the measurement chamber. When a DUT, that is or is included on a substrate, is tested at a low temperature, systems and methods are selected to heat the substrate in a dry environment, at least partially isolated from the measurement chamber, to at least a temperature above the dew point and/or the frost point of the ambient environment.

Abstract: Systems and methods for providing wafer access in a wafer processing system are disclosed herein. The methods may include docking a first wafer cassette on the wafer processing system and removing a selected wafer from the first wafer cassette with the wafer processing system. The methods further may include performing a process operation on the selected wafer with the wafer processing system and undocking the first wafer cassette from the wafer processing system while performing the process operation. The methods also may include docking a second wafer cassette (which may be the same as or different from the first wafer cassette) on the wafer processing system, inventorying the second wafer cassette with the wafer processing system, and/or subsequently placing the selected wafer in the second wafer cassette. The systems may include wafer processing systems that include a controller that is programmed to perform at least a portion of the methods.

Abstract: High frequency interconnect structures, electronic assemblies that utilize high frequency interconnect structures, and methods of operating the same. The high frequency interconnect structures include a plurality of dielectric waveguides and are configured to communicatively connect a plurality of transmitters with a plurality of receivers and to convey a plurality of signals therebetween. The plurality of signals may include a plurality of electromagnetic waves and may have a frequency of at least 200 GHz. The high frequency interconnect structures further may be configured to decrease a potential for crosstalk between a first signal that is conveyed by a first dielectric waveguide of the plurality of dielectric waveguides and a second signal that is conveyed by a second dielectric waveguide of the plurality of dielectric waveguides, such as through control of a passband of the first dielectric waveguide relative to the second dielectric waveguide and/or the use of a crosstalk mitigation structure.

Abstract: Probe head assemblies, components of probe head assemblies, test systems including the probe head assemblies and/or components thereof, and methods of operating the same. The probe head assemblies are configured to convey a plurality of test signals to and/or from a device under test and include a space transformer, a contacting assembly, and a riser that spatially separates the space transformer from the contacting assembly and conveys the plurality of test signals between the space transformer and the contacting assembly. The contacting assembly may include a frame that defines an aperture and has a coefficient of thermal expansion that is within a threshold difference of that of the device under test, a flexible dielectric body that is attached to the frame, maintained in tension by the frame, and extends across the aperture, and a plurality of conductive probes. The plurality of conductive probes may include a dual-faceted probe tip.

Abstract: Improved methods and systems for imaging are provided. Specifically, systems and methods for extending the range of a digital zoom are provided in which an imaging system provides continuous magnification over a plurality of interleaved optical pathways and digital zooming imagers. Systems and methods of centering an image as the field of view changes, and for masking out undesirable obstacles from a magnified image are also provided.

Abstract: The invention relates to a prober for checking and testing electronic semiconductor components and methods of using the same. The prober comprises at least two checking units, each of which is equipped with a chuck, probes, and a positioning unit, and each of which is assigned to a machine control system and a process control system. The prober further comprises a loading unit for automatically loading both testing units and an additional loader for manually loading at least one of the testing units, a user interface, and a module control system for controlling the process control systems and/or the machine control systems and the loading unit. The user interface can optionally be connected to at least one of the process control systems or the module control system by means of a switching device of the prober.

Abstract: The invention generally relates to a method and device for contacting contact areas (22) with probe tips (18) in a tester. The contact areas (22), which are arranged on a substrate (6), and the probe tips (18) are positioned relative to each other and then brought in contact with each other by an advancing motion. In order to detect a secure contact for each of the probe tips (18), the contacting between the probe tips (18) and the contact areas (22) is observed from at least two observation directions (34), which include an observation angle ? in a range of 0 to 180°.

Abstract: Resilient electrical interposers that may be utilized to form a plurality of electrical connections between a first device and a second device, as well as systems that may utilize the resilient electrical interposers and methods of use and/or fabrication thereof. The resilient electrical interposers may include a resilient dielectric body with a plurality of electrical conduits contained therein. The plurality of electrical conduits may be configured to provide a plurality of electrical connections between a first surface of the electrical interposer and/or the resilient dielectric body and a second, opposed, surface of the electrical interposer and/or the resilient dielectric body. The systems and methods disclosed herein may provide for improved vertical compliance, improved contact force control, and/or improved dimensional stability of the resilient electrical interposers.