Patents Assigned to Cavium, Inc.
  • Method to measure edge-rate timing penalty of digital integrated circuits
    Patent number: 9740807
    Abstract: Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing delay error between the two models. The timing delay error may then be used to correct timing delays computed by static-timing models for similar unbalanced circuit elements within a more complex digital circuit.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: August 22, 2017
    Assignee: Cavium, Inc.
    Inventors: Nitin Mohan, Vasudevan Kandadi
  • Method of dynamically renumbering ports and an apparatus thereof
    Patent number: 9742694
    Abstract: Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port renumbering scheme that dynamically assigns a relative port number for each port assigned to that pipe. The dynamic port renumbering scheme allows for internal parallelism without increasing the total amount of state space required for the ports on the network chip.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: August 22, 2017
    Assignee: Cavium, Inc.
    Inventors: Vishal Anand, Vamsi Panchagnula
  • Method for storing and retrieving packets in high bandwidth and low latency packet processing devices
    Patent number: 9736069
    Abstract: A packet processor includes a header processor and a packet memory. A receive direct memory access block is configured to receive a packet with a header and a payload and to route the header to the header processor and to route the payload to the packet memory such that the header processor begins processing of the header while the payload is loaded into packet memory.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 15, 2017
    Assignee: Cavium, Inc.
    Inventors: Tsahi Daniel, Enric Musoll, Dan Tu
  • Apparatus and method for processing alternately configured longest prefix match tables
    Patent number: 9729447
    Abstract: A network switch includes a memory configurable to store alternate table representations of an individual trie in a hierarchy of tries. A prefix table processor accesses in parallel, using an input network address, the alternate table representations of the individual trie and searches for a longest prefix match in each alternate table representation to obtain local prefix matches. The longest prefix match from the local prefix matches is selected. The longest prefix match has an associated next hop index base address and offset value. A next hop index processor accesses a next hop index table in the memory utilizing the next hop index base address and offset value to obtain a next hop table pointer. A next hop processor accesses a next hop table in the memory using the next hop table pointer to obtain a destination network address.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: August 8, 2017
    Assignee: Cavium, Inc.
    Inventors: Weihuang Wang, Mohan Balan, Nimalan Siva, Zubin Shah
  • Fast hardware switchover in a control path in a network ASIC
    Patent number: 9729338
    Abstract: A multicast destination table contains a list of links. The list of links includes the main link that is currently in use and alternate links to reach the same destination. The links in the list of links are ordered based on a metric. Each of the links is stored as an entry in the multicast destination table. A multicast replication engine traverses the list of links until an enabled link in the list of links is reached, and replicates a packet according to data associated with the enabled link in the list of links.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: August 8, 2017
    Assignee: Cavium, Inc.
    Inventors: Gerald Schmidt, Harish Krishnamoorthy, Tsahi Daniel
  • Apparatus and method for software enabled access to protected hardware resources
    Patent number: 9729320
    Abstract: A semiconductor includes a set of protected hardware resources, where at least one protected hardware resource stores a secure key. The semiconductor also includes a computation kernel and a memory to store a resource enablement module executed by the computation kernel. The resource enablement module selectively enables a protected hardware resource in response to a delivered key corresponding to the secure key.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: August 8, 2017
    Assignee: Cavium, Inc.
    Inventors: Amer Haider, Muhammad Raghib Hussain, Richard Eugene Kessler
  • Lookup front end packet input processor
    Patent number: 9729527
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 8, 2017
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Gregg A. Bouchard
  • METHODS AND APPARATUS FOR PROVIDING AN FFT ENGINE USING A RECONFIGURABLE SINGLE DELAY FEEDBACK ARCHITECTURE
    Publication number: 20170220523
    Abstract: Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus includes a radix-2 (R2) single delay feedback (SDF) stage that generates a radix-2 output and a radix-3 (R3) SDF stage that generates a radix-3 output. The apparatus also includes one or more radix-2 squared (R2?2) SDF stages that generate a radix-4 output. The apparatus further includes a controller that configures a sequence of radix stages selected from the R2, R3, and R2?2 stages based on an FFT point size to form an FFT engine. The FFT engine receives input samples at a first stage of the sequence and generate an FFT output result that is output from a last stage of the sequence. The sequence includes no more than one R3 stage.
    Type: Application
    Filed: December 14, 2016
    Publication date: August 3, 2017
    Applicant: Cavium, Inc.
    Inventors: Mehran Nekuii, Hong Jik Kim
  • Method and apparatus for aligning signals
    Patent number: 9721627
    Abstract: A method and corresponding apparatus for aligning a data signal with a corresponding clock signal include oversampling the data signal based on the corresponding clock signal and generating corresponding data samples. An indication of skew between the data signal and the corresponding clock signal is detected based on data samples. A variable delay line coupled to the data signal is then adjusted based on the indication of skew detected. According to at least one example implementation, the data signal is oversampled based on the corresponding clock signal and multiple time-shifted versions of the corresponding clock signal. At least one signal of the corresponding clock signal and the multiple time-shifted versions of the corresponding clock signal is employed in sampling the data signal at a potential transition edge of the data signal.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: August 1, 2017
    Assignee: Cavium, Inc.
    Inventors: Thucydides Xanthopoulos, David D. Lin, Edward W. Thoenes
  • Managing reuse information in caches
    Patent number: 9720773
    Abstract: Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses; translating from the intermediate physical addresses to physical addresses; determining reuse information for memory pages based on estimated reuse of cache lines of data stored within the memory pages; storing the determined reuse information independently from: (1) any bits used to indicate virtual addresses, (2) any bits used to indicate intermediate physical addresses, and (3) any bits used to indicate physical addresses; and using the stored reuse information to store cache lines in a selected group of multiple groups of cache lines of a first cache.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 1, 2017
    Assignee: Cavium, Inc.
    Inventor: Shubhendu Sekhar Mukherjee
  • Apparatus and method for distributed instruction trace in a processor system
    Patent number: 9703669
    Abstract: One disclosed embodiment provides an integrated circuit that has a plurality of processors and a plurality of processor trace collection logic units. Each processor trace collection logic unit corresponds with, and is operatively coupled to, one of the processors. A separate filtering logic unit is operatively coupled to the plurality of processor trace collection logic units. In some embodiments of the integrated circuit, each processor trace collection logic unit is operative to continuously collect processor trace information from a corresponding operatively coupled processor. Each filtering logic unit is operative to monitor the continuous processor trace information for occurrence of a predetermined condition, and to store some of the processor trace information to memory in response to occurrence of that condition.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: July 11, 2017
    Assignee: CAVIUM, Inc.
    Inventors: Gerald Lampert, David Kravitz, Bryan W. Chin
  • Method and system for compressing data for a translation look aside buffer (TLB)
    Patent number: 9703722
    Abstract: An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: July 11, 2017
    Assignee: CAVIUM, INC.
    Inventors: Anna Kujtkowski, Wilson P. Snyder, II
  • Apparatus and method for media access control scheduling with a priority calculation hardware coprocessor
    Patent number: 9706564
    Abstract: An apparatus includes a Media Access Control (MAC) scheduler to generate a priority value calculation request with a specified formula and a list of metrics. A hardware based priority value calculation coprocessor services the priority value calculation request in accordance with the specified formula and the list of metrics.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 11, 2017
    Assignee: Cavium, Inc.
    Inventors: Muhammad Raghib Hussain, Vishal Murgai
  • Method and apparatus for power control
    Patent number: 9703351
    Abstract: Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: July 11, 2017
    Assignee: Cavium, Inc.
    Inventors: David A. Carlson, Richard E. Kessler
  • Methods and Apparatus for Twiddle Factor Generation for Use with a Programmable Mixed-Radix DFT/IDFT Processor
    Publication number: 20170195281
    Abstract: Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates a base vector values based on the selected TFSV, and a twiddle column generator that generates a twiddle vector from the base vector.
    Type: Application
    Filed: November 9, 2016
    Publication date: July 6, 2017
    Applicant: Cavium, Inc.
    Inventors: Yuanbin Guo, Hong Jik Kim
  • METHODS AND APPARATUS FOR A VECTOR MEMORY SUBSYSTEM FOR USE WITH A PROGRAMMABLE MIXED-RADIX DFT/IDFT PROCESSOR
    Publication number: 20170192935
    Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.
    Type: Application
    Filed: October 12, 2016
    Publication date: July 6, 2017
    Applicant: Cavium, Inc.
    Inventors: Yuanbin Guo, Hong Jik Kim
  • Methods and Apparatus for Providing a Programmable Mixed-Radix DFT/IDFT Processor Using Vector Engines
    Publication number: 20170192936
    Abstract: A programmable vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values is disclosed. In an exemplary embodiment, an apparatus includes a memory bank and a vector data path pipeline coupled to the memory bank. The apparatus also includes a configurable mixed radix engine coupled to the vector data path pipeline. The configurable mixed radix engine is configurable to perform a selected radix computation selected from a plurality of radix computations. The configurable mixed radix engine performs the selected radix computation on data received from the memory bank through the pipeline to generate a radix result. The apparatus also includes a controller that controls how many radix computation iterations will be performed to compute an N-point DFT/IDFT based on a radix factorization.
    Type: Application
    Filed: September 21, 2016
    Publication date: July 6, 2017
    Applicant: Cavium, Inc.
    Inventors: Yuanbin Guo, Hong Jik Kim
  • Methods and Apparatus for Configuring a Front End to Process Multiple Sectors with Multiple Radio Frequency Frames
    Publication number: 20170195900
    Abstract: Methods and apparatus for configuring a front end to process multiple sectors with multiple radio frequency frames. In an exemplary embodiment, a method includes decoding instructions included in a job description list, and configuring one or more processing functions of a transceiver to process a radio signal associated with a selected sector based on the decoded instructions. The configuration of the processing functions is synchronized according to time control instructions included in the job description list.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 6, 2017
    Applicant: Cavium, Inc.
    Inventors: Mehran Nekuii, Frank Henry Worrell, Hong Jik Kim
  • Phase measurement and correction circuitry
    Patent number: 9698808
    Abstract: A circuit provides for phase adjustment of an offset clock pair, and includes an analog stage and a digital stage. The analog stage provides for generating an adjusted offset clock pair and detecting a phase difference between the adjusted offset clock pair. The digital stage operates to quantify the phase difference and provide a command for further adjusting the phase of the adjusted offset clock pair, at the analog stage, towards a target phase offset value.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: July 4, 2017
    Assignee: Cavium, Inc.
    Inventors: Scott E. Meninger, Lu Wang
  • Filtering translation lookaside buffer invalidations
    Patent number: 9697137
    Abstract: A filter includes filter entries, each corresponding to a mapping between a virtual memory address and a physical memory address and including a presence indicator indicative which processing elements have the mapping present in their respective translation lookaside buffers (TLBs). A TLB invalidation (TLBI) instruction is received for a first mapping. If a first filter entry corresponding to the first mapping exists in the filter, the plurality of processing elements are partitioned into a first partition of zero or more processing elements that have the first mapping present in their TLBs and a second partition of zero or more processing elements that do not have the first mapping present in their TLBs based on the presence indicator of the first filter entry. The TLBI instruction is sent to the processing elements included in the first partition, and not those in the second partition.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: July 4, 2017
    Assignee: CAVIUM, INC.
    Inventor: Shubhendu Sekhar Mukherjee