Patents Assigned to Cavium, Inc.
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Patent number: 9690590Abstract: Executing instructions in a processor includes: selecting or more instructions to be issued together in the same clock cycle of the processor from among a plurality of instructions, the selected one or more instructions occurring consecutively according to a program order; and executing instructions that have been issued, through multiple execution stages of a pipeline of the processor. The executing includes: determining a delay assigned to a first instruction, and sending a result of a first operation performed by the first instruction in a first execution stage to a second execution stage, where the number of execution stages between the first execution stage and the second execution stage is based on the determined delay.Type: GrantFiled: October 15, 2014Date of Patent: June 27, 2017Assignee: CAVIUM, INC.Inventor: David Albert Carlson
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Patent number: 9692715Abstract: In an embodiment an interface unit includes a transmit pipeline configured to transmit egress data, and a receive pipeline configured to receive ingress data. At least one of the transmit pipeline and the receive pipeline being may be configured to provide shared resources to a plurality of ports. The shared resources may include at least one of a data path resource and a control logic resource.Type: GrantFiled: February 21, 2014Date of Patent: June 27, 2017Assignee: Cavium, Inc.Inventors: Shahe H. Krakirian, Paul G. Scrobohaci, Daniel A. Katz
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Patent number: 9684606Abstract: Managing a plurality of translation lookaside buffers (TLBs) includes: issuing, at a first processing element, a first instruction for invalidating one or more TLB entries associated with a first context in a first TLB associated with the first processing element. The issuing includes: determining whether or not a state of an indicator indicates that all TLB entries associated with the first context in a second TLB associated with a second processing element are invalidated; if not: sending a corresponding instruction to the second processing element, causing invalidation of all TLB entries associated with the first context in the second TLB, and changing a state of the indicator; and if so: suppressing sending of any corresponding instructions for causing invalidation of any TLB entries associated with the first context in the second TLB to the second processing element.Type: GrantFiled: November 14, 2014Date of Patent: June 20, 2017Assignee: CAVIUM, INC.Inventors: Richard Eugene Kessler, Shubhendu Sekhar Mukherjee, Mike Bertone
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Publication number: 20170171854Abstract: Methods and apparatuses for providing soft and blind combining for PUSCH CQI processing are disclosed. In an exemplary embodiment, a method includes generating a plurality of hypothetical rank indicator (RI) values associated with a user equipment (UE), and concurrently soft-combining channel quality information (CQI) and RI information associated with the UE that is contained in a received subframe of symbols. The RI information is soft-combined to generate a soft-combined RI bit stream and the CQI information is soft-combined based on the plurality of hypothetical RI values to generate a plurality of soft-combined CQI bit streams, respectively. The method also includes decoding the soft-combined RI bit stream to generate a decoded RI value, and decoding a selected soft-combined CQI bit stream based on the decoded RI value to generate a decoded CQI value.Type: ApplicationFiled: May 19, 2016Publication date: June 15, 2017Applicant: Cavium, Inc.Inventors: SABIH GUZELGOZ, Hongjik Kim, Tejas Maheshbhai Bhatt, Fariba Heidari
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Publication number: 20170170930Abstract: Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing. In an exemplary embodiment, a method includes soft-combining acknowledgement (ACK) bits received from a UE that are contained in a received sub-frame of symbols. The ACK bits are soft-combined using a plurality of scrambling sequences to generate a plurality of hypothetical soft-combined ACK bit streams. The method also includes receiving a parameter that identifies a selected scrambling sequence to be used. The method also includes decoding a selected hypothetical soft-combined ACK bit stream to generate a decoded ACK value, wherein the selected hypothetical soft-combined ACK bit stream is selected from the plurality of hypothetical soft-combined ACK bit streams based on the parameter.Type: ApplicationFiled: December 14, 2016Publication date: June 15, 2017Applicant: Cavium, Inc.Inventors: Sabih Guzelgoz, Hong Jik Kim, Tejas Maheshbhai Bhatt, Fariba Heidari
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Patent number: 9678159Abstract: A master controller includes: an interface to a CPU, an input port configured to receive a digital signal, and an output port configured to transmit a digital signal. Slave controllers each include: an interface to a device, an input port configured to receive a digital signal, and an output port configured to transmit a digital signal. A first chain bridge includes: a first set of input and output ports that couple the first chain bridge to a first chain of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of the first chain include the master controller, and a second set of input and output ports that couple the first chain bridge to a second chain of nodes each coupled to neighboring nodes by conductor paths in a closed loop, where the nodes of the second chain include multiple slave controllers.Type: GrantFiled: March 4, 2015Date of Patent: June 13, 2017Assignee: CAVIUM, INC.Inventor: Ethan Frederick Robbins
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Patent number: 9678717Abstract: In an embodiment, a method include, in a hardware processor, producing, by a block of hardware logic resources, a constrained randomly generated or pseudo-randomly generated number (CRGN) based on a bit mask stored in a register memory.Type: GrantFiled: November 13, 2015Date of Patent: June 13, 2017Assignee: CAVIUM, INC.Inventors: Wilson P. Snyder, II, Varada Ogale, Anna Kujtkowski, Albert Ma
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Patent number: 9678779Abstract: A method and a system embodying the method for a data plane virtualization, comprising assigning each of at least one data plane a unique identifier; providing a request comprising an identifier of one of the at least one data plane together with an identifier of a virtual resource assigned to a guest; determining validity of the provided request in accordance with the identifier of the one of the at least one data plane and the identifier of the virtual resource assigned to the guest; and processing the request based on the determined validity of the request are disclosed.Type: GrantFiled: July 31, 2014Date of Patent: June 13, 2017Assignee: Cavium, Inc.Inventor: Wilson Parkhurst Snyder, II
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Patent number: 9680742Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: GrantFiled: February 28, 2014Date of Patent: June 13, 2017Assignee: Cavium, Inc.Inventors: Joseph B. Tompkins, Brian Robert Folsom, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins, Krupa Sagar O. S. Mylavarapu, Mahesh Dorai, Nagaraj G. Shirali, Ranjith Kumar V. Hallur
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Patent number: 9671844Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.Type: GrantFiled: September 26, 2013Date of Patent: June 6, 2017Assignee: Cavium, Inc.Inventors: David A. Carlson, Richard E. Kessler
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Patent number: 9673753Abstract: In an embodiment, a voltage-controlled oscillator circuit includes a gain element and an LC resonator coupled with the gain element, the LC resonator including an inductor section and a capacitor section. The capacitor section has at least two branches connected in parallel and a voltage control input for tuning the LC resonator. Any of the at least two branches is selected from the group of DC-coupled and AC-coupled. Characteristics of the two branches and bias voltages of the AC-coupled branches are selected to provide a tuning curve of the voltage-controlled oscillator circuit that is approximately linear.Type: GrantFiled: January 19, 2016Date of Patent: June 6, 2017Assignee: CAVIUM, INC.Inventors: Omer O. Yildirim, JingDong Deng, Scott E. Meninger
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Patent number: 9665508Abstract: A method and an apparatus embodying the method for converting interrupts into scheduled events, comprising receiving an interrupt at an interrupt controller; determining a vector number for the interrupt; determining properties of an interrupt work in accordance with the vector number; and scheduling the interrupt work in accordance with the properties of the interrupt work, is disclosed.Type: GrantFiled: December 26, 2013Date of Patent: May 30, 2017Assignee: Cavium, Inc.Inventors: Wilson Parkhurst Snyder, II, Lei Tian
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Patent number: 9665300Abstract: A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to each virtual system on chip.Type: GrantFiled: June 24, 2016Date of Patent: May 30, 2017Assignee: Cavium, Inc.Inventors: Muhammad Raghib Hussain, Rajan Goyal, Richard Kessler
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Patent number: 9665505Abstract: A motherboard includes multiple sockets, each socket configured to accept an integrated circuit. A first integrated circuit in a first socket includes one or more cores and at least one buffer. A second integrated circuit in a second socket includes one or more cores and at least one buffer. Communication circuitry transfers messages to buffers of integrated circuits coupled to different sockets. A first core on the first integrated circuit is configured to send messages corresponding to multiple types of instructions to a second core on the second integrated circuit through the communication circuitry. The buffer of the second integrated circuit is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores on the first integrated circuit at the same time, and still have enough storage space for one or more instructions of a first type.Type: GrantFiled: November 14, 2014Date of Patent: May 30, 2017Assignee: CAVIUM, INC.Inventors: Shubhendu Sekhar Mukherjee, David Asher, Bradley Dobbie, Thomas Hummel, Daniel Dever
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Patent number: 9667446Abstract: A condition code approach for comparing dimension match data of a rule with corresponding data in a key is provided. The approach includes, given dimension match data divided into first and second portions, comparing the first portion with a corresponding first portion of data in a key and setting a first condition code based on the comparison. The approach further includes comparing the second portion with a corresponding second portion of key data and setting a second condition code based on the comparison. The approach further includes determining whether the dimension match data is equal to, greater than, or less than the corresponding data in the key based on the first and second condition codes, and returning a response indicating whether the data matches based on the determination.Type: GrantFiled: January 8, 2014Date of Patent: May 30, 2017Assignee: CAVIUM, INC.Inventor: Frank Worrell
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Patent number: 9652171Abstract: A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if needed or a portion of the control path memory to be used by the datapath subsystem if needed.Type: GrantFiled: March 30, 2015Date of Patent: May 16, 2017Assignee: Cavium, Inc.Inventors: Enrique Musoll, Weihuang Wang
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Patent number: 9652505Abstract: An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different interpretations. By generating state for the node, the graph of nodes does not become exponential. It also allows a user function to be called upon reaching a node, which can perform any desired user tasks, including modifying the input data or position.Type: GrantFiled: April 21, 2016Date of Patent: May 16, 2017Assignee: Cavium, Inc.Inventors: Muhammad R. Hussain, David A. Carlson, Gregg A. Bouchard, Trent Parker
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Patent number: 9647947Abstract: A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a routing appliance coupled to a network compiles data structures to process keys associated with a particular block mask register (BMR) of a plurality of BMRs. For each BMR of the plurality of BMRs, the processor identifies at least one of or a combination of: i) at least a portion of a field of a plurality of rules and ii) a subset of fields of the plurality of fields to be masked. The processor also builds at least one data structure used to traverse a plurality of rules based on the identified at least one of or a combination of: i) at least a portion of a field of a plurality of rules and ii) a subset of fields of the plurality of fields to be masked.Type: GrantFiled: January 10, 2014Date of Patent: May 9, 2017Assignee: CAVIUM, INC.Inventors: Rajan Goyal, Kenneth Bullis
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Patent number: 9645790Abstract: The present disclosure relates to an add and decode hardware logic circuit for adding two n bit inputs, A and B. A series of n logic stages are each configured to perform a first operation of propagating a result of a preceding stage on the condition that the sum of A[m] and B[m] is equal to 0, wherein 0<=m<n, perform a second operation of performing a bitwise left shift by 2m of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 1, or perform a third operation of performing a bitwise left shift by 2m+1 of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 2. An output at the last stage provides a decoded sum of the inputs A and B.Type: GrantFiled: November 11, 2014Date of Patent: May 9, 2017Assignee: Cavium, Inc.Inventors: Edward Beckman, Nitin Mohan
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Patent number: 9645941Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.Type: GrantFiled: September 26, 2013Date of Patent: May 9, 2017Assignee: CAVIUM, INC.Inventors: Shubhendu S. Mukherjee, Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis
