Abstract: An injector for injecting at least one substance into eggs, comprising an injection body that can be moved between a raised position and an injection position, and equipped with an injection conduit, an injection needle, a guiding and protection tube of the needle subject to elastic stress by elastic means to an idle position and capable of being moved towards a retracted position by pressing its distal end against an egg when the injector is in the injection position. The injector is equipped with control means for controlling the supply of said injection conduit with at least one substance, said tube cooperating with said control means to disable the supply of said injection conduit when said tube is in the idle position and to enable the supply of said conduit when said tube is in the retracted position.

Abstract: The present invention relates to an automatic egg examining device for differentiating between fertilized eggs and unfertilized eggs, comprising emission means (3), which comprise, for each egg to be examined, at least one coherent laser source forming a coherent optical beam (31) directed at an egg (9) to be examined, reception means (4), which receive the light flux passing through the egg, and data processing means (7), which process the light flux received by said reception means in order to determine the state—fertilized or unfertilized—of the egg.

Abstract: The invention relates to new compositions comprising an aldosterone antagonist according to a particular posology for the treatment of heart failure in non-human mammal animals.

Abstract: A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to one or more arbitrary functional units external to the processor core. The interface is to provide the arbitrary functional units with access to the register file.

Abstract: Method for the qualitative and semi-quantitative detection of a ligand in a sample of a medium to be tested, by (1) diluting at least one lyophilized reaction medium in said sample, (2) incubating the sample in order to carry out an immunoenzymatic method, and (3) observing the resulting colouration.

Abstract: A method for the generation of addresses of successive pairs of input data values of stages of a Fast Fourier Transform calculation stored contiguously in a memory includes initializing at most once per stage a first base address pointer to an address of a first input data value of an initial butterfly calculation of the stage and a second base address pointer to an address of a second input data value of the initial butterfly calculation, and initializing at most once per stage a first constant and a second constant. Pairs of input data values of successive butterfly calculations in the stage are then addressed using the first base address pointer, the second base address pointer, the first constant and the second constant.

Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.

Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.

Abstract: A functional unit includes one or more instances of arithmetic circuitry for calculating averages. Each instance of arithmetic circuitry includes first, second and third adders, each having first and second inputs and an output that is a sum of the first and second inputs and a carry-in bit. An output of the first adder is coupled to a first input of the third adder, and an output of the second adder is coupled to a second input of the third adder. The arithmetic circuitry is able to calculate an arithmetic operation on a set of four inputs. The arithmetic operation is fully determined by control bits and may be: an average of two values (with or without rounding by 1), an average of four values (with or without rounding by 1 or 2), or a sum of four values.

Abstract: A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a writing memory access unit writes the data to the destination memory array according to a destination access template.

Abstract: Charge from a charge pump of a PLL is dumped to a loop filter of the PLL. The dumped charge is temporarily stored in a capacitor, between the charge pump and the loop filter. A voltage of the capacitor is shifted, while temporarily storing the dumped charge. Other embodiments are also described and claimed.

Abstract: A 3-input adder/subtractor unit, having a first input for receiving a first operand A, a second input for receiving a second operand B, and a third input for receiving a third operand C. An add/subtract unit includes a control input for receiving a user-specified opcode, a first 3-to-2 compressor for receiving a respective least significant bit of said operands or its complement, and a Half Adder coupled to the first 3-to-2 compressor and responsive to an output thereof and to said opcode for outputting a least significant bit of a sum equal to A+B+C or A+B?C or A?B+C or A?B?C. A plurality of 3-to-2 compressors each in respect of remaining bits of the operands receive a respective bit of the operands or its complement, and a 2-input adder coupled to the 3-to-2 compressors receive respective carry and save outputs thereof and computing respective bits of the sum apart from the least significant bit.

Abstract: A filter couples an output of a phase detector to an input of a voltage controlled oscillator. The filter has a first capacitor and a switch capacitor resistor that is in series with the first capacitor, between the first capacitor and the output of the phase detector. The switch capacitor resistor is to display a resistance that is obtained by switching back and forth a second capacitor to the first capacitor and to the phase detector output. Other embodiments are also described and claimed.

Abstract: A mobile telephony handset has a wireless communications transceiver for exchanging signals with a base station, and a positioning receiver for receiving coded ranging signals from a satellite-based positioning system. The handset is configured such that the positioning receiver is activated only periodically to perform a position fix using the ranging signals and between such active periods is in a power-saving condition. Each position fix includes a respective time measurement in which a precision time indication referenced to the positioning system reference time source is recorded and saved. The handset includes calibration means, which generates a calibrated time reference for performing each of a plurality of new such position fixes.

Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.

Abstract: A system for generating and storing trace bits for Viterbi decoding of binary convolution codes includes at least one arithmetic logic unit (ALU) for determining the trace bits, and a first register and a second register for storing the trace bits. The first register stores a first half of a series of trace bits for N states in sequential order and the second register stores a second half of the series in sequential order. A binary convolution decoder having multiple stages each having N states includes at least one arithmetic logic unit (ALU), a first register and a second register, and a storage device. The at least one ALU determines trace bits for each of the N states for each of the multiple stages. The first and second registers store trace bits of at least a portion of one stage. The storage device has memory cells. For each of the multiple stages, a group of at least one memory cell stores the N trace bits in sequential order.

Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.

Abstract: A method for indexing a plurality of ordered elements stored in bit-reversed order in a first and a second memory space, the first memory space indexed by a first memory index denoting memory positions in the first memory space, the second memory space indexed by a second memory index denoting memory positions in the second memory space, the logical position of the elements within the ordered elements indexed by an element index, the method including bit-reversing the element index of a selected element, locating the selected element as being in the first memory space where the MSB of the bit-reversed index equals 0 and the second memory space where the MSB of the bit-reversed index equals 1, and locating the position of the selected element within the MSB-located memory space at the memory index of the MSB-located memory space that corresponds to the non-MSB bits of the bit-reversed index.

Abstract: A method that calculates a threshold for a signal according to a first bandwidth if the signal is greater than the threshold plus a first value or if the signal is less than the threshold minus the first value. The method also calculates the threshold for the signal according to a second bandwidth if the signal is not greater than the threshold plus the first value and if the signal is not less than the threshold minus the first value. The first bandwidth is greater than the second bandwidth. Various apparati that perform the method are also described.

Abstract: An image compression method is provided including separating an image into a plurality of color channel sub-images processing each of the color channel sub-images by sub-sampling the sub-image transform coding the sub-sampled sub-image decoding the transform-coded image forming a plurality of square groupings of pixels in the decoded image predicting a value for a pixel within each of the x-shaped groupings determining a prediction error for each predicted pixel value within each of the square groupings coding the prediction error forming a plurality of at least partly diamond-shaped groupings of pixels in the decoded image predicting a value for a pixel within each of the diamond-shaped groupings and combining each of the processed color channel sub-images with the coded prediction errors, thereby forming a compressed image.