Patents Assigned to Chartered Semiconductor Manufacturing Ltd.
  • Patent number: 8643119
    Abstract: A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: February 4, 2014
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing LTD
    Inventors: Zhijiong Luo, Huilong Zhu, Yung Fu Chong, Hung Y. Ng, Kern Rim, Nivo Rovedo
  • Patent number: 8623714
    Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: January 7, 2014
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd., Samsung Electronics Co., Ltd.
    Inventors: Jae-Eun Park, Weipeng Li, Deleep R. Nair, M. Dean Sciacca, Voon-Yew Thean, Ava Wan, Dong-Hun Lee, Yong-Meng Lee
  • Patent number: 8461009
    Abstract: Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: June 11, 2013
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.
    Inventors: Atul C. Ajmera, Christopher V. Baiocco, Xiangdong Chen, Wenzhi Gao, Young Way Teh
  • Patent number: 8236699
    Abstract: A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: August 7, 2012
    Assignees: Infineon North, Samsung Electronics Co., Ltd., International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd., Infineon Technologies AG
    Inventors: Byung-Goo Jeon, Sung-Chul Park, Nikki Edleman, Alois Gutmann, Fang Chen
  • Patent number: 8198194
    Abstract: Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: June 12, 2012
    Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing Ltd., International Business Machines Corporation
    Inventors: Jong Ho Yang, Hyung-rae Lee, Jin-Ping Han, Chung Woh Lai, Henry K. Utomo, Thomas W. Dyer
  • Publication number: 20120074519
    Abstract: An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate.
    Type: Application
    Filed: September 26, 2011
    Publication date: March 29, 2012
    Applicant: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Alfred Yeo, Kai Chong Chan
  • Patent number: 8138055
    Abstract: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: March 20, 2012
    Assignees: Infineon Technologies AG, Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jin-Ping Han, Alois Gutmann, Roman Knoefler, Jiang Yan, Chris Stapelmann, Jingyu Lian, Yung Fu Chong
  • Patent number: 8106462
    Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: January 31, 2012
    Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc., Infineon Technologies North America Corp., Chartered Semiconductor Manufacturing Ltd.
    Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
  • Publication number: 20110278645
    Abstract: Methods (and semiconductor substrates produced therefrom) of fabricating (n?1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n?1 SDOI substrates.
    Type: Application
    Filed: July 26, 2011
    Publication date: November 17, 2011
    Applicant: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Lee Wee Teo, Chung Foong Tan, Shyue Seng Tan, Elgin Quek
  • Patent number: 8058176
    Abstract: Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: November 15, 2011
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corproation, Advanced Micro Devices Corporation, Chartered Semiconductor Manufacturing Ltd., Infineon Technologies AG
    Inventors: Wan-jae Park, Kaushik Arun Kumar, Joseph Edward Linville, Anthony David Lisi, Ravi Prakash Srivastava, Hermann Willhelm Wendt
  • Patent number: 8026166
    Abstract: Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: September 27, 2011
    Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing Ltd.
    Inventors: Griselda Bonilla, Tien Cheng, Lawrence A. Clevenger, Stephan Grunow, Chao-Kun Hu, Roger A. Quon, Zhiguo Sun, Wei-tsui Tseng, Yiheng Xu, Yun Wang, Hyeok-sang Oh
  • Publication number: 20110227136
    Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 22, 2011
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD., CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Jae-Eun Park, Weipeng Li, Deleep R. Nair, M. Dean Sciacca, Voon-Yew Thean, Ava Wan, Dong-Hun Lee, Yong-Meng Lee
  • Patent number: 8017472
    Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. Isolation regions are formed that include a stress-altering material at least partially lining a trench formed within a workpiece. The isolation regions include an insulating material disposed over the stress-altering material.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: September 13, 2011
    Assignees: Infineon Technologies AG, Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jin-Ping Han, Yung Fu (Alfred) Chong
  • Patent number: 8012839
    Abstract: A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: September 6, 2011
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jinping Liu, Alex K H See, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 7994010
    Abstract: A process for fabricating a semiconductor device, such as a strained-channel transistor, includes forming epitaxial regions in a substrate in proximity to a gate electrode in which the surface profile of the epitaxial regions is defined by masking sidewall spacers adjacent the gate electrode. The epitaxial regions are formed by depositing an epitaxial material into cavities selectively etched into the semiconductor substrate on either side of the gate electrode. The masking sidewall spacers limit the thickness of the epitaxial deposited material in proximity of the gate electrode, such that the upper surface of the epitaxial material is substantially the same as the principal surface of the semiconductor substrate. Doped regions are formed in the channel region beneath the gate electrode using an angled ion beam, such that doping profiles of the implanted regions are substantially unaffected by surface irregularities in the epitaxially-deposited material.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 9, 2011
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lee Wee Teo, Alain Chan, Chung Foong Tan, Elgin Kiok Boone Quek
  • Publication number: 20110169096
    Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 14, 2011
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR, INC., INFINEON TECHNOLOGIES NORTH AMERICA CORP., CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
  • Patent number: 7977185
    Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: July 12, 2011
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.
    Inventors: Brian J. Greene, Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Siddhartha Panda, Kern Rim, Young Way Teh
  • Publication number: 20110163356
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths.
    Type: Application
    Filed: January 4, 2010
    Publication date: July 7, 2011
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Ming ZHU, Chun Shan YIN, Elgin QUEK, Shyue Seng TAN
  • Publication number: 20110156121
    Abstract: A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Lee Wee Teo, Chunshan Yin, Shyue Seng Tan, Ch√ľng Foong Tan, Jae Gon Lee, Elgin Quek, Purakh Raj Verma
  • Publication number: 20110157567
    Abstract: A liquid immersion scanning exposure system utilizes an immersion liquid confined within a watertight lens hood having a base portion formed from a solid optical element. During operation, a bottom portion of a lens assembly is disposed within the immersion liquid and the solid optical element is placed upon a photoresist material or layer (to be patterned). The lens assembly moves laterally through the immersion liquid parallel to the photoresist material. Because the solid optical element separates the immersion liquid from the photoresist material and does not move relative to the photoresist material, the photoresist material does not contact with the immersion liquid and the solid optical element and is not susceptible to damage or scratching by the solid optical element.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Applicant: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Wenzhan Zhou, Sia Kim Tan, Lei Yuan, Meisheng Zhou