Patents Assigned to Chartered Semiconductor Manufacturing Ltd.
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Patent number: 7829422Abstract: A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to subsequently processing, such as curing medium used to form voids in an ultralow-k dielectric layer.Type: GrantFiled: December 22, 2006Date of Patent: November 9, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Johnny Widodo, Huang Liu, Sin Leng Lim
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Publication number: 20100276815Abstract: A method of manufacture of an integrated circuit communication system including providing a semiconductor wafer; and fabricating a cross-over current mirror driver on the semiconductor wafer for generating a crossing point at a reference voltage.Type: ApplicationFiled: April 29, 2009Publication date: November 4, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: On Auyeung, Fei Xu
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Patent number: 7824968Abstract: First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.Type: GrantFiled: July 17, 2006Date of Patent: November 2, 2010Assignee: Chartered Semiconductor Manufacturing LtdInventors: Sanford Chu, Yisuo Li, Guowei Zhang, Purakh Raj Verma
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Publication number: 20100270670Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit substrate having a non-active side and an active side; forming a recess in the integrated circuit substrate from the non-active side exposing a first contact and a second contact with the first contact and the second contact along the active side; forming a first via, having a first via extension extended beyond the non-active side and an opening at the non-active side, within the recess; forming a barrier liner within the opening with the barrier liner exposed beyond the non-active side; and forming a second via over the barrier liner and within the opening of the first via with the second via exposed beyond the non-active side.Type: ApplicationFiled: April 24, 2009Publication date: October 28, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Alfred Yeo, Kai Chong Chan
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Patent number: 7816909Abstract: Methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure are disclosed. In one embodiment, the test structure includes a first test transistor including a first stress level; and at least one second test transistor having a substantially different second stress level. A testing circuit can then be used to characterize the mechanical stress level by comparing performance of the first test transistor and the at least one second test transistor. The type of test structure depends on the integration scheme used. In one embodiment, at least one second test transistor is provided with a substantially neutral stress level and/or an opposite stress level from the first stress level. The substantially neutral stress level may be provided by either rotating the transistor, removing the stressed layer causing the stress level or de-stressing the stressed layer causing the stress layer.Type: GrantFiled: July 29, 2008Date of Patent: October 19, 2010Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing LtdInventors: Victor Chan, Khee Yong Lim
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Patent number: 7816274Abstract: The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the effected regions of the semiconductor devices depending upon the population density of device components. Differing separation distances are obtained by selectively forming sidewall spacers on device components, such as MOS transistor gate electrodes, in which the sidewall spacers have a relatively small width in regions having a relatively high density of device components, and a relatively larger width in regions having a relatively low density of device components. By varying the separation distance of strain-inducing structures from the effected components, uniform electrical performance is obtained in the various components of the devices in an integrated circuit regardless of the component population density.Type: GrantFiled: March 27, 2008Date of Patent: October 19, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Lee Wee Teo, Chung Foong Tan, Alain Chan, Elgin Kiok Boone Quek
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Publication number: 20100258868Abstract: A method of manufacture of an integrated circuit system includes: providing a second layer between a first layer and a third layer; forming an active device over the third layer; forming the third layer to form an island region underneath the active device; forming the second layer to form a floating second layer with an undercut beneath the island region; and depositing a fourth layer around the island region and the floating second layer.Type: ApplicationFiled: April 13, 2009Publication date: October 14, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Chunshan Yin, Lee Wee Teo, Chung Foong Tan, Jae Gon Lee
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Patent number: 7803704Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: GrantFiled: August 22, 2008Date of Patent: September 28, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Bei Chao Zhang, Chim Seng Seet, Juan Boon Tan, Fan Zhang, Yong Chiang Ee, Bo Tao, Tong Qing Chen, Liang Choo Hsia
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Patent number: 7800182Abstract: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.Type: GrantFiled: November 20, 2006Date of Patent: September 21, 2010Assignees: Infineon Technologies AG, Chartered Semiconductor Manufacturing, Ltd.Inventors: Jin-Ping Han, Alois Gutmann, Roman Knoefler, Jiang Yan, Chris Stapelmann, Jingyu Lian, Yung Fu Chong
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Publication number: 20100230744Abstract: A method of forming a semiconductor device is presented. A substrate prepared with a second gate is provided. The second gate is processed to form a second gate with a rounded corner and a first gate is formed on the substrate. The first gate is adjacent to and overlaps a portion of the second gate and the rounded corner.Type: ApplicationFiled: March 11, 2009Publication date: September 16, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Timothy Phua, Bangun Indajang, Dong Kyun Sohn
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Publication number: 20100230765Abstract: An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a channel exhibiting the characteristics of stress memorization.Type: ApplicationFiled: May 20, 2010Publication date: September 16, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Elgin Kiok Boone Quek, Pradeep Ramachandramurthy Yelehanka
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Patent number: 7795104Abstract: A method for forming device structures having a variation in electrical conductivity includes forming a device structure and a radiation absorbing layer overlying the device structure. The radiation absorbing layer has a spatial variation and radiation absorbing characteristics, such that upon irradiating the device structure, the radiation absorbing layer attenuates the intensity of the radiation so that a variation in dopant activation takes place within the device structure. Accordingly, device structures are formed having a variation in electrical resistance independent of the physical size of the device structures.Type: GrantFiled: February 13, 2008Date of Patent: September 14, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Elgin Kiok Boone Quek, Lee Wee Teo, Shyue Seng Tan
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Patent number: 7795680Abstract: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.Type: GrantFiled: December 7, 2007Date of Patent: September 14, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Huang Liu, Alex K. H. See, James Lee, Johnny Widodo, Chung Woh Lai, Wenzhi Gao, Zhao Lun, Shailendra Mishra, Liang-Choo Hsia
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Patent number: 7790617Abstract: A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form a copper interconnect in the interconnect opening. The copper interconnect is over polished to form a depression. We form metal silicide layer over the copper interconnect using a low temperature sputtering process. We can form a cap layer over the metal silicide layer.Type: GrantFiled: November 12, 2005Date of Patent: September 7, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Yeow Kheng Lim, Wei Lu, Liang Choo Hsia, Jyoti Gupta, Chim Seng Seet, Hao Zhang
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Publication number: 20100221926Abstract: A system for and method of processing an article such as a semiconductor wafer is disclosed. The wafer includes first and second surface which are segmented into a plurality of first and second zones. The first surface of the wafer, for example, on which devices or ICs are formed is processed by, for example, laser annealing while the second surface is heated with a backside heating source. Corresponding zones on the first and second surfaces are processed synchronously to reduce variations of post laser anneal thermal budge across the wafer.Type: ApplicationFiled: March 2, 2009Publication date: September 2, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Chyiu Hyia Poon, Alex Kh See, Meisheng Zhou
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Patent number: 7785950Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.Type: GrantFiled: November 10, 2005Date of Patent: August 31, 2010Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd, Chartered Semiconductor Manufacturing LtdInventors: Sunfei Fang, Jun Jung Kim, Zhijiong Luo, Hung Y. Ng, Nivo Rovedo, Young Way Teh
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Publication number: 20100213544Abstract: A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask.Type: ApplicationFiled: February 23, 2009Publication date: August 26, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Junwen LIU, Purakh Raj VERMA, Yan JIN, Baofu ZHU
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Publication number: 20100213543Abstract: A method of forming a device is presented. The method includes providing a substrate prepared with an active device region. The active device region includes gate stack layers of a gate stack including at least a gate electrode layer over a gate dielectric layer. A first mask is provided on the substrate corresponding to the gate. The substrate is patterned to at least remove portions of a top gate stack layer unprotected by the first mask. A second mask is also provided on the substrate with an opening exposing a portion of the first mask and the top gate stack layer. A channel well is formed by implanting ions through the opening and gate stack layers into the substrate.Type: ApplicationFiled: July 10, 2009Publication date: August 26, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Guo Wei ZHANG, Purakh Raj VERMA
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Patent number: 7781895Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.Type: GrantFiled: June 17, 2009Date of Patent: August 24, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
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Publication number: 20100206818Abstract: The present invention relates to semiconductor processing. In particular, it relates to a tunable ultrasonic filter and a method of using the same for more effective separation of large particles from slurry. In one embodiment a standing wave is produced in the filter and large particles are accumulated at the nodes of the standing waves while the slurry is flowed out of the filter.Type: ApplicationFiled: February 19, 2009Publication date: August 19, 2010Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Lup San Leong, Feng Zhao, Benfu Lin, Haigou Huang, Xianbin Wang