Abstract: A control method used in a constant on-time switching converter includes: judging whether the switching converter enters into an ultrasonic mode; turning ON the low-side switch to discharge the output capacitor when the switching converter enters into the ultrasonic mode; generating an additional slope compensation signal during the discharge of the output capacitor; comparing a feedback signal indicative of the output voltage of the switching circuit with the sum of a reference voltage and the additional slope compensation signal; turning OFF the low-side switch and turning ON the high-side switch when the feedback signal decreases to reach the sum of the reference voltage and the additional slope compensation signal.

Abstract: A soft start circuit for a switching converter, the soft start circuit has an internal soft start voltage generating circuit, an amplifier circuit and a buffer circuit, the internal soft start voltage generating circuit provides an internal soft start voltage, the amplifier circuit has a first input terminal receiving the internal soft start voltage, a second input terminal receiving a soft start reference signal and an output terminal, the buffer circuit has an input terminal coupled to the output terminal of the amplifier circuit and an output terminal providing the soft start reference signal. An external soft start capacitor coupled to the output terminal of the amplifier circuit is charged to provide an external soft start voltage, and the soft start reference signal is provided based on the internal soft start voltage and the external soft start voltage.

Abstract: A controller used in a multi-phase switching converter, including: a bias current generator that generates a plurality of bias current signals; a temperature balance modulating circuit that generates a plurality of on time signals based on the plurality of the bias current signals; and a logic circuit that generates a plurality of control signals based on the plurality of on time signals. The plurality of the control signals is used to control a plurality of switching circuits of the multi-phase switching converter.

Abstract: The present disclosure discloses a field effect transistor (“FET”), a termination structure and associated method for manufacturing. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench and a guard ring region located underneath the bottom of the termination trench in the semiconductor layer. Each termination trench is lined with a termination insulation layer, and is filled with a first conductive spacer and a second conductive spacer respectively against an inner sidewall and an outer sidewall of the termination trench and spaced apart from each other with a space, and a dielectric layer filling the space between the first and the second spacers.

Abstract: A light-emitting element driver system has a power conversion circuit, a second switch and a control circuit, the power conversion circuit has a primary circuit, a transformer, a first rectified circuit and a second rectified circuit, the second rectified circuit provides a first signal, the second switch has a first terminal coupled to an output terminal of the first rectified circuit and a second terminal to provide a second signal, when a dimming signal is in a first state, the control circuit provides a first control signal to control the power conversion circuit based on the first signal, and meanwhile provides a second control signal to control the second switch based on the second signal.

Abstract: A PFC circuit includes: a switching circuit having a power switch; an on time control circuit for controlling an on time period of the power switch; a first off time control circuit; a second off time control circuit; and a logic circuit selectively controls the power switch working under CCM or DCM; when working under CCM, the first off time control circuit controls an off time period of the power switch and when working under DCM, the second off time control circuit controls the off time period of the power switch.

Abstract: A control circuit for a switching converter having a comparison circuit, a synchronization unit, an ON-time control circuit and a logic unit, the comparison circuit provides a comparison signal based on a reference signal and an output signal of the switching converter, the synchronization unit provides a first synchronization signal and a second synchronization signal based on a first clock signal, a second clock signal and the comparison signal, the first synchronizing signal is generated by synchronizing the comparison signal with the first clock signal, the second synchronizing signal is generated by synchronizing the comparison signal with the second clock signal, the ON-time control circuit provides an ON-time control signal, the logic unit provides a switching control signal to control the switching converter based on the first synchronization signal, the second synchronization signal and the ON-time control signal.

Abstract: A ripple suppression circuit has a filter circuit and a follower circuit. The filter circuit has a first input terminal coupled to a signal source to receive a ripple signal and an output terminal to output a filter signal which is the sum of the average value of the ripple signal and a positive bias signal. The follower circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the signal source to receive the ripple signal, the second input terminal is coupled to the output terminal of the filter circuit to receive the filter signal, the follower circuit provides an output signal at the output terminal, the output signal at least partially follows the filter signal.

Abstract: A switching converter with slope compensation circuit, the slope compensation circuit has a first voltage source, a first operation circuit, a first switch, a first capacitor, a second switch and a first controlled current source.

Abstract: A LED driver, a LED driving method and a controller for LED driver are discussed in the present invention. The LED driver detects the phase of the input signal which is phase cut by a triac from a pre-E-transformer. The LED driver regulates the current flowing through the LED strings by varying the phase of the input signal.

Abstract: An EEPROM memory cell with a coupler region is disclosed. The coupler region has a well and at least one feeder region formed in the well. The at least one feeder region is configured to provide majority carriers to a channel region defined in the well so that a portion of the channel region adjoining the top surface of the coupler region is inverted during an erase operation.

Abstract: A boost PFC converter, a method and a control circuit used for boost PFC converter are discussed in the present invention. The boost PFC converter decreases the switching frequency when a line voltage is around zero, so that the whole operating efficiency is not decreased.

Abstract: A voltage detecting circuit used with a switching converter. The switching converter having an energy storage component, a first power switch and a second switch. The voltage detecting circuit has a sample and hold circuit configured to sample and hold the voltage at the connection node of the energy storage component and the first power switch when the first power switch is OFF and the second power switch is ON; and an average circuit configured to average the sampled voltage during a switching period to generate a detecting signal in proportional to the output voltage of the switching converter.

Abstract: A power supply system has a current source configured to provide an output current, a load supplied by the current source, and a current ripple suppression circuit. The current ripple suppression circuit has a first end and a second end, wherein the first end of the current ripple suppression circuit is coupled to the load, and the second end of the current ripple suppression circuit is coupled to a reference ground; wherein the current ripple suppression circuit is configured to suppress the current ripple in the output current and adaptively adjust the output current of the current source at a predetermined current level.

Abstract: A converter circuit has an error amplifier to provide an error signal; a proportional amplifier to provide a gain signal according the error signal and an output voltage of the converter circuit; a first comparator, generating a pulse signal according to the gain signal and a comparison signal; and a timer, generating a timing signal according to the pulse signal to indicate the on time and the off time of the converter circuit; and wherein either the gain signal or the comparison signal comprises a ramp component, and wherein the on time of the converter circuit is constant.

Abstract: A switching charger having a control circuit configured to provide a control signal; a power stage turned ON and OFF by the control signal; an inductor coupled between the power stage and a load; and an output capacitor coupled in parallel with the load; a current sense circuit integrated to the control circuit to sense a current flowing through the power stage.

Abstract: A converter control circuit for converting an input voltage to an output voltage comprises: an error amplifier, coupled to an output voltage or a feedback output signal from the output voltage, and a reference signal, operable to generate an error signal accordingly; a ramp signal generator, generating a first ramp signal and a second ramp signal; a first comparator, coupled to the error signal and the first ramp signal, operable to generate a first comparing signal accordingly; a second comparator, coupled to the error signal and the second ramp signal, operable to generate a second comparing signal accordingly; and a control signal generator, coupled to the first comparing signal and the second comparing signal, operable to generate a control signal to turn switches in the converter circuit ON and OFF accordingly.

Abstract: A switching converter and a load regulation compensation module for improving load regulation accuracy of the switching converter. The switching converter regulates its output voltage through controlling a switch module to switch on and off based on a first reference signal and a feedback signal indicative of the output voltage. The on and off switching of the switch module generates a switching current, resulting in an average offset voltage between an internal reference ground and a package ground pin of the switching converter. The load regulation compensation module is configured to monitor the switching current, and to compensate a second reference signal having a bandgap reference voltage referenced to the internal reference ground based on the monitored switching current to generate the first reference signal, so that the average offset voltage is substantially cancelled out from the first reference signal with respect to the package ground pin.

Abstract: A timing circuit used in lighting systems includes a first logic circuit, a first counter, a latching circuit and a judging circuit. The first logic circuit generates a first logic signal and a second logic signal based on a falling edge of a detecting signal. The first counter generates a first counting signal and a second counting signal based on the second logic signal, wherein the counting period of the first counting signal is longer than that of the second counting signal. The latching circuit samples and holds the first counting signal based on the first logic signal and provides a third counting signal. The judging circuit detects whether the second counting signal is equal to the third counting signal and provides a timing signal.

Abstract: A semiconductor device having an ESD protection structure and a method for forming the semiconductor device. The ESD protection structure is formed atop a termination area of the substrate and is electrically coupled between a source metal and a gate metal of the semiconductor device. The ESD protection structure has a first portion adjacent to the source metal, a second portion adjacent to the gate metal and a middle portion between and connecting the first portion and the second portion, wherein the middle portion has a first thickness greater than a second thickness of the first portion and the second portion. Such an ESD protection structure is beneficial to the formation of interlayer vias which are formed to couple the ESD protection structure to the source metal and the gate metal.