Patents Assigned to Chengdu Sicore Semiconductor Corp. Ltd.
  • Patent number: 11791808
    Abstract: Various NLTL frequency comb generator embodiments are disclosed for broadband impedance matching to generate an output signal comprising broadband harmonics of an input signal. The NLTL frequency comb generator comprises a plurality of segments cascaded in series, with each segment comprising a series inductor and a non-linear shunt capacitor. The non-linear shunt capacitor may couple to corresponding series inductors in the same polarity. A broadband biasing circuit feeds a DC bias or DC ground to the non-linear shunt capacitors for broadband input and output impedance matching. The broadband biasing circuit may be a low pass filter to prevent RF signal from leaking through the biasing circuit. The NLTL frequency comb generator, the broadband biasing circuit, and an output DC blocking capacitor may be integrated in a single chip in a compact packaging to achieve a broadband input/output impedance matching without relying on external lumped matching components.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: October 17, 2023
    Assignee: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Publication number: 20230317682
    Abstract: Various embodiments for die stacking are disclosed in the present disclosure for improved performance in RF circuit integration and packaging. In various layouts, a first die may be flipped and stacked on a second die via one or more bumping pillars coupled between the dies. The bumping pads may be disposed on the first die, the second die, or both. The bumping pads may comprise ground bumping pads for ground connection, RF signal bumping pads for cross-die RF signal transmission, and/or control bumping pads for biasing or logic control. Furthermore, the ground bumping pads and the RF signal bumping pad may form a ground-signal-ground pad structure for smooth RF signal transmission. The present embodiments may integrate a silicon-based die with an III-V semiconductor-based die together for a small form factor package with the well-defined ground to handle RF signals over millimeter-wave frequencies at high power levels.
    Type: Application
    Filed: June 8, 2022
    Publication date: October 5, 2023
    Applicant: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Publication number: 20230317635
    Abstract: Various embodiments for guard ring arrangement on low-k dielectric materials to reduce moisture ingress effect are disclosed in the present disclosure. Embodiments of a double guard ring structure comprising an outer guard ring and an inner guard ring are disclosed. The double guard ring structure has an outer slit and an inner slit opposite to each other for an open loop structure to avoid inductive coupling during RF signal transmission. With lengthened moisture ingress paths, the double guard ring structure enables easy implementation. Disclosed also are embodiments of a closed guard ring structure in a flipped RF chip. The closed guard ring has one or more ground bumping pads disposed inside and grounded via bumping pillars to a top ground layer of a substrate. Furthermore, the ground bumping pads and the RF signal bumping pad may form a ground-signal-ground (GSG) pad structure for a smooth RF transmission.
    Type: Application
    Filed: June 8, 2022
    Publication date: October 5, 2023
    Applicant: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Patent number: 11742303
    Abstract: Various system embodiments for millimeter-wave chip packaging are disclosed in the present disclosure for smooth millimeter wave signal transition and good multi-channel signal isolation. The chip packaging features a substrate and a chip electrically connected using a plurality of metal pillars. A signal pillar and surrounding metal pillar may form a ground-signal-ground (GSG) pillar structure. A chip coplanar waveguide (CPW) structure may be formed on the chip around a signal path. A substrate CPW structure may also be form around a signal strip, which is electrically connected to the signal path. Characteristic impedances of the GSG pillar structure, the chip CPW structure and the substrate CPW structure may be within a predetermined range of each other to ensure smooth millimeter wave signal transition with minimum signal loss or distortion.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 29, 2023
    Assignee: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Publication number: 20220157747
    Abstract: Various system embodiments for millimeter-wave chip packaging are disclosed in the present disclosure for smooth millimeter wave signal transition and good multi-channel signal isolation. The chip packaging features a substrate and a chip electrically connected using a plurality of metal pillars. A signal pillar and surrounding metal pillar may form a ground-signal-ground (GSG) pillar structure. A chip coplanar waveguide (CPW) structure may be formed on the chip around a signal path. A substrate CPW structure may also be form around a signal strip, which is electrically connected to the signal path. Characteristic impedances of the GSG pillar structure, the chip CPW structure and the substrate CPW structure may be within a predetermined range of each other to ensure smooth millimeter wave signal transition with minimum signal loss or distortion.
    Type: Application
    Filed: December 11, 2020
    Publication date: May 19, 2022
    Applicant: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Patent number: 11239848
    Abstract: Various embodiments of the invention relate to calibrate a wideband segmented Voltage Controlled Oscillator (VCO). Upon initial calibration, information of frequency spanning ranges of each segment in the VCO may be saved into a memory. When the VCO is used or activated, a microcontroller reads data from the memory and applied selected information accordingly. The initial calibration involves a frequency sweep process beginning from a first segment with an initial frequency and records any lock detection (LD) signal to the MCU when a frequency/phase lock is engaged from an unlock status or interrupted from a lock status. With the LD signals, frequency bands of the segments may be calibrated, adjusted for temperature compensated, and finalized after associating adjacent segment frequency overlap zone. A frequency band for a segment may be further segmented into multiple sub-bands with corresponding charge pump currents designated respectively for improved phase lock loop phase noise performance.
    Type: Grant
    Filed: May 8, 2021
    Date of Patent: February 1, 2022
    Assignee: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventors: Cemin Zhang, Xuanli Huang
  • Publication number: 20210320645
    Abstract: Various embodiments of the invention relate to high linearity RF circuits that may operate or function consistently under various levels of voltage, current or power. Embodiments of a diode module comprising cascaded diodes and connecting bias branches are disclosed for improved linearity of RF circuits. The diode module may comprise multiple diodes reversely coupled in series. Additionally, the diode module further comprises connecting bias branches coupled in parallel with diode pairs. Such configuration of reversely cascaded diodes coupled with alternatively connecting bias branches increases the robustness of the diode module to handle high input voltage or power from the RF path, thus provides enhanced linearity for the RF circuit as compared to single diode configuration.
    Type: Application
    Filed: May 18, 2020
    Publication date: October 14, 2021
    Applicant: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Patent number: 11146248
    Abstract: Various embodiments of the invention relate to high linearity RF circuits that may operate or function consistently under various levels of voltage, current or power. Embodiments of a diode module comprising cascaded diodes and connecting bias branches are disclosed for improved linearity of RF circuits. The diode module may comprise multiple diodes reversely coupled in series. Additionally, the diode module further comprises connecting bias branches coupled in parallel with diode pairs. Such configuration of reversely cascaded diodes coupled with alternatively connecting bias branches increases the robustness of the diode module to handle high input voltage or power from the RF path, thus provides enhanced linearity for the RF circuit as compared to single diode configuration.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: October 12, 2021
    Assignee: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Publication number: 20210313967
    Abstract: Various embodiments of the invention relate to attenuators with reduced temperature variation. By coordinating first-order resistance temperature (FORT) coefficients of resistors, embodiments of attenuator or attenuator cells are capable of achieving desired attenuation with reduced or minimized temperature variation. Such achievements in reducing temperature variation may be obtained without relying on resistors with large negative FORT coefficients. Attenuator cells may be configured as T-type attenuator cells, ?-type attenuator cells, bridged-T attenuator cells, or shunt attenuators with various FORT coefficient combinations for the resistors incorporated within the attenuator cells. Furthermore, various attenuator cells may be cascaded together into a digital step attenuator with the temperature variation of those cells compensating or offsetting each other for an overall minimum temperature variation.
    Type: Application
    Filed: May 18, 2020
    Publication date: October 7, 2021
    Applicant: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventors: Cemin Zhang, Zhengwei Deng
  • Patent number: 11121702
    Abstract: Various embodiments of the invention relate to attenuators with reduced temperature variation. By coordinating first-order resistance temperature (FORT) coefficients of resistors, embodiments of attenuator or attenuator cells are capable of achieving desired attenuation with reduced or minimized temperature variation. Such achievements in reducing temperature variation may be obtained without relying on resistors with large negative FORT coefficients. Attenuator cells may be configured as T-type attenuator cells, ?-type attenuator cells, bridged-T attenuator cells, or shunt attenuators with various FORT coefficient combinations for the resistors incorporated within the attenuator cells. Furthermore, various attenuator cells may be cascaded together into a digital step attenuator with the temperature variation of those cells compensating or offsetting each other for an overall minimum temperature variation.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 14, 2021
    Assignee: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventors: Cemin Zhang, Zhengwei Deng
  • Patent number: 10992394
    Abstract: Embodiments of channel parameters consistency calibration methods in multi-channel phased array systems are disclosed. The method comprises a reference channel calibration step and a calibration step for other channels to be calibrated. The reference channel calibration step comprises selecting one channel as a reference channel and performing a full state calibration on the reference channel to generate full state control data set S(A). Parameters to be calibrated in the calibration step of the uncalibrated channel may be a phase shift amount or an attenuation amount. The calibration step for the uncalibrated channel comprises a calibration under at least one specified parameter group. Compared with the conventional calibration methods, the present calibration method greatly shortens the calibration time, reduces the required data storage capacity, thereby improves efficiency for completing the consistence calibration of the parameters for multi-channel phased array systems.
    Type: Grant
    Filed: January 18, 2020
    Date of Patent: April 27, 2021
    Assignee: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Patent number: 10833647
    Abstract: Various embodiments of the invention relate to a high performance analog bandpass filter (BPF) with improved performance in suppressing parasitic passband. The BPF comprises a first loss-pass filter (LPF) coupled to a first RF port, a second LPF coupled to a second RF port, and at least one high-pass module coupled in series between the first LPF and the second LPF for band-pass tuning. A resonant circuit is composed by a shunt capacitor from the LPF, a shunt inductor from the high-pass module and a series inductor from the LPF coupled in between. Such layout empowers the LPFs triple functions: to function as a low-pass filter, to participate in resonant circuit for center frequency tuning of the BPF, and to suppress parasitic resonance. Such a triple-function of the LPFs gives the BPF an improvement in a compact but effective topology.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 10, 2020
    Assignee: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventors: Cemin Zhang, Qiling Zheng, Rong Zhang
  • Patent number: 10804846
    Abstract: Various embodiments of the invention relate to a Multi-Band Voltage Controlled Oscillator (VCO). The multi-band VCO features a coupled-inductor based resonator. The resonator comprises a primary path and a secondary path inductively coupled to the primary path. The primary path comprises multiple LC tuning stages coupled in series with each stage having an adjustable capacitor and a primary inductor inductively coupled to the secondary path. The secondary path comprises multiple secondary inductors inductively coupled to respective primary inductors in the primary path. Furthermore, the secondary path comprises a plurality of controllable switches which are controlled to switch ON or OFF simultaneously to engage/disengage the inductive coupling between the primary path and the secondary path. Incorporating multiple LC tuning stages lowers voltage swing across each tuning stages, thus minimizing phase noise caused by nonlinearity in the resonator.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: October 13, 2020
    Assignee: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Patent number: 10686419
    Abstract: Various embodiments of the invention relate to a tunable gain equalizer to enable a RF output with constant gain over a wide frequency band. The tunable gain equalizer comprises a series path formed by a plurality of adjustable capacitors coupled in series, and two shunt paths coupled to the series path. The adjustable capacitors may be varactors coupled to a biasing voltage for capacitance adjustment. The shunt paths comprise inductors to enable a positive gain slope to compensate negative gain slope of RF amplifiers. The shunt paths may be bridged by one or more branches connected between the two shunt paths. The bridged branches provide a higher tunable gain slope amount and a better input/output matching. By making the biasing voltage of the tunable gain equalizer temperature dependent, the tunable gain equalizer is able to generate a temperature dependent gain slope to offset the temperature variation influence.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: June 16, 2020
    Assignee: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Publication number: 20200036353
    Abstract: Various embodiments of the invention relate to a tunable gain equalizer to enable a RF output with constant gain over a wide frequency band. The tunable gain equalizer comprises a series path formed by a plurality of adjustable capacitors coupled in series, and two shunt paths coupled to the series path. The adjustable capacitors may be varactors coupled to a biasing voltage for capacitance adjustment. The shunt paths comprise inductors to enable a positive gain slope to compensate negative gain slope of RF amplifiers. The shunt paths may be bridged by one or more branches connected between the two shunt paths. The bridged branches provide a higher tunable gain slope amount and a better input/output matching. By making the biasing voltage of the tunable gain equalizer temperature dependent, the tunable gain equalizer is able to generate a temperature dependent gain slope to offset the temperature variation influence.
    Type: Application
    Filed: March 26, 2019
    Publication date: January 30, 2020
    Applicant: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Patent number: 10541648
    Abstract: Present invention relate to a wideband signal source. The wideband signal source comprises a voltage controlled oscillator (VCO), a first buffer and a programmable frequency extender. The VCO outputs a signal with at least N:1 frequency tuning ratio, with N being an integer or a non-integer number larger than 1. The frequency extender receives the signal via the buffer to generate a final output, which has a wider frequency band than the signal. The buffer isolates the final output from interfering VCO for VCO operation stability. The frequency extender comprises at least a 1/N frequency divider, which matches the N:1 frequency tuning ratio of the signal, such that the final output has a gapless frequency band wider than the VCO output signal.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: January 21, 2020
    Assignee: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Publication number: 20200014362
    Abstract: Various embodiments of the invention relate to a high performance analog bandpass filter (BPF) with improved performance in suppressing parasitic passband. The BPF comprises a first loss-pass filter (LPF) coupled to a first RF port, a second LPF coupled to a second RF port, and at least one high-pass module coupled in series between the first LPF and the second LPF for band-pass tuning. A resonant circuit is composed by a shunt capacitor from the LPF, a shunt inductor from the high-pass module and a series inductor from the LPF coupled in between. Such layout empowers the LPFs triple functions: to function as a low-pass filter, to participate in resonant circuit for center frequency tuning of the BPF, and to suppress parasitic resonance. Such a triple-function of the LPFs gives the BPF an improvement in a compact but effective topology.
    Type: Application
    Filed: March 26, 2019
    Publication date: January 9, 2020
    Applicant: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventors: Cemin Zhang, Qiling Zheng, Rong Zhang
  • Publication number: 20190372524
    Abstract: Various embodiments of the invention relate to a Multi-Band Voltage Controlled Oscillator (VCO). The multi-band VCO features a coupled-inductor based resonator. The resonator comprises a primary path and a secondary path inductively coupled to the primary path. The primary path comprises multiple LC tuning stages coupled in series with each stage having an adjustable capacitor and a primary inductor inductively coupled to the secondary path. The secondary path comprises multiple secondary inductors inductively coupled to respective primary inductors in the primary path. Furthermore, the secondary path comprises a plurality of controllable switches which are controlled to switch ON or OFF simultaneously to engage/disengage the inductive coupling between the primary path and the secondary path. Incorporating multiple LC tuning stages lowers voltage swing across each tuning stages, thus minimizing phase noise caused by nonlinearity in the resonator.
    Type: Application
    Filed: March 26, 2019
    Publication date: December 5, 2019
    Applicant: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Publication number: 20190348949
    Abstract: Present invention relate to a wideband signal source. The wideband signal source comprises a voltage controlled oscillator (VCO), a first buffer and a programmable frequency extender. The VCO outputs a signal with at least N:1 frequency tuning ratio, with N being an integer or a non-integer number larger than 1. The frequency extender receives the signal via the buffer to generate a final output, which has a wider frequency band than the signal. The buffer isolates the final output from interfering VCO for VCO operation stability. The frequency extender comprises at least a 1/N frequency divider, which matches the N:1 frequency tuning ratio of the signal, such that the final output has a gapless frequency band wider than the VCO output signal.
    Type: Application
    Filed: June 21, 2018
    Publication date: November 14, 2019
    Applicant: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang
  • Patent number: 10454419
    Abstract: The invention discloses a voltage controlled oscillator (VCO) based on hybrid resonator, including a hybrid resonator and a negative resistance circuit, wherein the hybrid resonator includes the first LC series resonance branch, the second LC series resonance branch and the third LC series resonance branch. The first LC series resonance branch and the second LC series resonance branch forms a parallel structure, in which one end of the said parallel structure is grounded while the other end is connected to the third LC series resonance branch, and the other end of the third LC series resonance branch is connected to the negative resistance circuit. The resonance frequency of the first LC series resonance branch is lower than that of the second LC series resonance branch. The invented VCO can effectively improve the phase noise, especially maintain a good phase noise with the increase of the tuning frequency.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 22, 2019
    Assignee: Chengdu Sicore Semiconductor Corp. Ltd.
    Inventor: Cemin Zhang