Patents Assigned to Chipbond Technology Corporation
  • Patent number: 11812554
    Abstract: A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. The chip is mounted on the chip mounting area, a space exists between a first bump and a second bump of the chip, and there are no additional bumps between the first and second bumps. A first inner lead, a second inner lead, a first dummy lead and a second dummy lead of the circuit layer are located on the chip mounting area. The first and second inner leads are electrically connected to the first and second bumps respectively. The first dummy lead is connected to the first inner lead and adjacent to the first bump, and the second dummy lead is connected to the second inner lead and adjacent to the second bump.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 7, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Patent number: 11792923
    Abstract: A storage device of the present invention is provided to store flexible circuit packages, each of the flexible circuit packages includes an electronic component and two circuit portions warped at both sides of the electronic component, respectively. The storage device includes a first carrier and a second carrier. The first carrier includes first accommodation elements provided for placement of the flexible circuit packages, and the second carrier includes a first press portion and a second press portion. As the second carrier is placed on the first carrier, the first and second press portions are provided to press the two circuit portions warped upwardly toward the second carrier so as to reduce the warpage of the two circuit portions.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: October 17, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Shih-Chieh Chang, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11764090
    Abstract: A tray includes a body for placement of a component (e.g. electronic component) and a taker disposed on a bottom surface of the body. The taker is used to take a spacer and includes a first taking element and a second taking element. The first taking element includes a first connection portion and a first confinement portion, and the second taking element includes a second connection portion and a second confinement portion. An accommodation space is provided between the first and second connection portions and a passageway is provided between the first and second confinement portions. While the spacer is moved through the passageway and into the accommodation space, it is confined in the accommodation space by the first and second confinement portions such that the taker can take away the spacer to show another tray located under the spacer as the tray is removed.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: September 19, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Hsu-Chi Lee, Pi-Yu Peng, Chun-Te Lee
  • Patent number: 11651974
    Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: May 16, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chih-Ming Kuo, Lung-Hua Ho, You-Ming Hsu, Fei-Jain Wu
  • Patent number: 11606860
    Abstract: A flexible circuit board includes a flexible substrate, a chip and a patterned circuit layer. A surface of the flexible substrate is separated into a working area and a nonworking area according to a cutting line. The chip is disposed on the working area. The patterned circuit layer is disposed on the surface and includes signal transmission wires and bypass wires, the bypass wires are not electrically connected to the chip. Each of the bypass wires includes a bypass transmission portion located on the working area and an anti-peeling portion located on the nonworking area. A blank area exists between the anti-peeling area and the bypass transmission portion, and the cutting line passes through the blank area. A distance between 100 um and 400 um exists from the anti-peeling portion to the cutting line.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: March 14, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Gwo-Shyan Sheu, Hsin-Hao Huang, Yu-Chen Ma, Chia-Hsin Yen
  • Patent number: 11602047
    Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: March 7, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yin-Chen Lin, Ming-Hsiao Ke, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11581283
    Abstract: A flip chip package includes a circuit board, a chip and a solder layer. The chip is mounted on an inner bonding area of the circuit board. The solder layer is located between the circuit board and the chip for bonding bumps to inner leads and a T-shaped circuit unit is on the inner bonding area. The T-shaped circuit unit has a main part, a connection part, and a branch part. The connection part is connected to the main and branch parts, respectively. The main part extends along a lateral direction and the branch part extends outwardly along a longitudinal direction. The connection part is narrower than the main part in width so as to inhibit solder shorts caused by solder overflow on the branch part.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: February 14, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Patent number: 11522517
    Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 6, 2022
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Cheng-Hung Shih, Cheng-Fan Lin
  • Patent number: 11503698
    Abstract: A flexible circuit board includes a flexible substrate, an electronic component and a heat spreader. The electronic component and the heat spreader are disposed on a top surface and a bottom surface of the flexible substrate, respectively. The heat spreader includes a copper layer which contains more than or equal to 50% copper grains by volume with (1,0,0) crystallographic orientation.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: November 15, 2022
    Assignee: Chipbond Technology Corporation
    Inventors: Yi-Ling Hsieh, Pei-Ying Lee, Dong-Sheng Li
  • Patent number: 11350518
    Abstract: In a method of heat sink attachment, a heat-sink tape includes a plurality of heat sinks and a flexible carrier, and a holder is provided to allow the heat sinks on the moving heat-sink tape to peel from the flexible carrier and attach to a heat-sink mounting area of a moving circuit tape automatically and successively.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 31, 2022
    Assignee: Chipbond Technology Corporation
    Inventors: Chia-Sung Lin, Huan-Kai Chou, Chia-Hsin Yen, Wen-Fu Chou
  • Patent number: 11322437
    Abstract: A flip chip interconnection including a circuit board is disclosed. The circuit board includes a substrate, inner leads, a T-shaped circuit line and a dummy pattern. The inner leads, the T-shaped circuit line and the dummy pattern are located on an inner bonding area of the substrate. The T-shaped circuit line includes a main segment, a branch segment and a connection segment that is connected to the main segment and the branch segment. The main segment and the branch segment are extended along a lateral direction and a longitudinal direction, respectively. The dummy pattern is located between the connection segment and the inner leads.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 3, 2022
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Patent number: 11309238
    Abstract: A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate, the circuit area surrounds the chip mounting area. The chip is mounted on the chip mounting area of the top surface and includes a bump. The circuit layer is disposed on the top surface. A connection portion of the circuit layer extends across a first side of the chip mounting area and into the chip mounting area. A transmission portion of the circuit layer is located on the circuit area and electrically connected to the connection portion. A stress release portion of the circuit layer is located between the transmission portion and a second side of the chip mounting area and is a comb-shaped structure.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: April 19, 2022
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Patent number: 11234328
    Abstract: A circuit board disclosed in the present invention includes a substrate and a circuit layer. The circuit layer is formed on a surface of the substrate and includes at least one test circuit line. The test circuit line includes a main segment and a branch segment connected with each other. The branch segment is provided to be contacted with a test equipment for electrical test so as to protect the main segment from breaking during electrical test.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: January 25, 2022
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chia-En Fan, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11206735
    Abstract: A flexible circuit board includes a flexible light-permeable carrier, a circuit layer, a mark and a stiffener. The circuit layer and the mark are located on a top surface of the flexible light-permeable carrier. A predetermined area and a stiffener mounting area corresponding to each other are defined on the top surface and a bottom surface of the flexible light-permeable carrier, respectively. The mark is opaque to create a shadow mark having a longitudinal reference side and a lateral reference side on the bottom surface. The stiffener is adhered to the stiffener mounting area defined on the bottom surface by aligning with the longitudinal reference side and the lateral reference side of the shadow mark.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: December 21, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yin-Chen Lin, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11177206
    Abstract: A layout structure of double-sided flexible circuit board includes a flexible substrate having a first surface and a second surface, a first circuit layer and a second circuit layer. An inner bonding region is defined on the first surface and an inner supporting region is defined on the second surface according to the inner bonding region. The first circuit layer is located on the first surface and includes first conductive lines which each includes an inner lead located on the inner bonding region. The second circuit layer is located on the second surface and includes second conductive lines which each includes an inner supporting segment located on the inner supporting region. A width difference between any two of the inner supporting segment of the second conductive lines is less than 8 ?m.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 16, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chun-Te Lee, Chih-Ming Peng, Hui-Yu Huang, Yin-Chen Lin
  • Patent number: 11178756
    Abstract: A flexible circuit board includes a flexible light-permeable carrier, a circuit layer, a mark and a stiffener. The circuit layer and the mark are located on a top surface of the flexible light-permeable carrier. A predetermined area and a stiffener mounting area corresponding to each other are defined on the top surface and a bottom surface of the flexible light-permeable carrier, respectively. The mark is opaque to create a shadow mark having a longitudinal reference side and a lateral reference side on the bottom surface. The stiffener is adhered to the stiffener mounting area defined on the bottom surface by aligning with the longitudinal reference side and the lateral reference side of the shadow mark.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 16, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yin-Chen Lin, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11148864
    Abstract: The present invention discloses a storage container for electronic devices, especially for wafer frames. The storage container includes a body and a stop rod that is provided to open or close a pick-and-place path in the body. The pick-and-place path is open to allow the wafer frames placed in the body to be taken out when a recess of the stop rod is located in the pick-and-place path. On the contrary, the pick-and-place path is closed when a blocking part of the stop rod is located in the pick-and-place path so as to protect the wafer frames placed in the body from falling out from the storage container.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: October 19, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Cheng-Hung Shih, Tsuo-Yun Chu
  • Patent number: 11084684
    Abstract: A restriction device for preventing deformation of restriction plate of reel is disclosed. The restriction device includes a first circular restrictor, a second circular restrictor, a block member and a first push member. A clamping space exists between the first and second circular restrictors mounted on a shaft and is configured to accommodate a reel mounted on the shaft. The second circular restrictor is able to be moved on the shaft in an axial direction, the block member is fixed on the shaft and the first push member is placed between the block member and the second circular restrictor. The first push member is configured to apply a force to push the second circular restrictor toward the first circular restrictor to press a first restriction plate of the reel such that the deformation of the first restriction plate is prevented.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: August 10, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventor: Chung-Yi Chang
  • Patent number: 11056555
    Abstract: A semiconductor device having 3D inductor includes a first transverse inductor, a longitudinal inductor and a second transverse inductor. The first transverse inductor is formed on a first substrate, the second transverse inductor and the longitudinal inductor are formed on a second substrate. The second substrate is bonded to the first substrate to connect the first transverse inductor and the longitudinal inductor such that the first transverse inductor, the longitudinal inductor and the second transverse inductor compose a 3D inductor.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: July 6, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Cheng-Hung Shih, Nian-Cih Yang, Yi-Cheng Chen, Shang-Jan Yang
  • Patent number: 10999928
    Abstract: A circuit board electrically connected to a chip includes a substrate and a circuit layer. A first conductive line of the circuit layer includes a main line and a branch lead connected with each other. The branch lead provided to increase lead quantity for bonding with the chip includes an extension part and a bonding part which is used for bonding a bump of the chip. During thermal compression, gaps existing between the extension part and the main line and between the bonding part and the main line can prevent solder on the main line from flowing toward the bump and overflowing from the branch lead.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 4, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu