Abstract: A reconfigurable cache in a signal processor provides a cache optimized for texture mapping. In particular, the reconfigurable cache provides two-banks of memory during one mode of operation and a palettized map under a second mode of operation. In one implementation, the reconfigurable cache optimizes mip-mapping by assigning one texture map in one of the memory banks and a second texture map of a different resolution to the other memory bank. A special mapping pattern ("supertiling") between a graphical image to cache lines minimizes cache misses in texture mapping operations.

Abstract: A method of rendering 3-D graphical image data suitable for use in interactive 3-D applications is provided, which reduces the amount of time required to perform the rendering. This is achieved by dynamically adjusting the resolution of the image depending upon the type of operation being performed. 3-D operations are performed at a reduced resolution, while 2-D operations (including display) are performed at full resolution. A method of dynamically enhancing/reducing resolution for image depth information (z-buffer data) is also provided.

Abstract: A software queue located in an offscreen portion of video memory is used as a large-capacity software queue for queuing messages to a graphics accelerator. Although the software queue is typically stored in a dynamic RAM (DRAM) memory, advantages of faster static RAM (SRAM) are achieved by shadowing some of the queuing information in SRAM. Usage of a large-capacity software queue in video DRAM memory and information shadowing in faster SRAM memory achieves an advantageous balance between throughput speed and queue size. The large-capacity of the software queue ensures that the queue is virtually never filled to capacity so that delays while awaiting free space in the queue are virtually never incurred. The capacity of the software queue is determined in software and is therefore adaptable to match a particular graphics application.

Abstract: A media engine is disclosed herein which incorporates into a single chip structure the seven multimedia functions of video, 2D graphics, 3D graphics, audio, FAX/modem, telephony, and video-conferencing. In accordance with the present invention, a media engine includes a signal processor which shares a memory with the CPU of the host computer and also includes a plurality of control modules each dedicated to one of the seven multi-media functions. The signal processor retrieves from this shared memory instructions placed therein by the host CPU and in response thereto causes the execution of such instructions via one of the on-chip control modules. The signal processor utilizes an instruction register having a movable partition which allows larger than typical instructions to be paired with smaller than typical instructions.

Abstract: A method for resampling includes convolving a given set of samples with the impulse response function of a low-pass filter. In this method, values of the impulse response required for the convolution calculation are computed at the time of resampling from a segmented polynomial approximating the impulse response.

Abstract: A system and method for dynamic resource management across tasks in real-time operating systems is disclosed. The system and method manage an arbitrary set of system resources and globally optimize resource allocation across system tasks in a dynamic fashion, according to a system specified performance model. The present invention provides a mechanism for system programmers to program tasks such that system performance will be globally optimized and dynamically managed over a system programmer-controllable set of system resources. The invention supports a mechanism for defining and managing arbitrary resources through a task resource utilization vector. Each task resource utilization vector contains an arbitrary number of task resource utilization records that contain quantities of system resources that each task qualitatively prefers to utilize while executing on the processor.

Abstract: A method and apparatus for producing a tone (e.g. for music) without use of a waveform memory and using a feedback loop. The feedback loop includes a waveform generator which calculates, in real time, a parabolic approximation to a sine wave. The feedback loop includes a delay phase differencer to eliminate hunting. The output waveform from the feedback loop is provided to a sine function generator which approximates a sine value using a third order polynomial, to provide the output tone.

Abstract: A system and method for stack-based processing of multiple real-time tasks operates on a net list of tasks which operate essentially simultaneously with system resources shared between tasks in a dynamic configuration. This system and method operate to control dispatching of messages which activate signal processing tasks, sequencing of processes activated by the messages and management of signal flow. Tasks are dynamically activated and deactivated in accordance with the specification by the net list by manipulating the task signals on the stack, thereby substantially reducing high-speed memory requirements of the system.

Abstract: A method for resampling includes convolving a given set of samples with the impulse response function of a low-pass filter. In this method, values of the impulse response required for the convolution calculation are computed at the time of resampling from a segmented polynomial approximating the impulse response. In one embodiment, the method is applied to provide musical tones of various pitches from a stored waveform.

Abstract: An arithmetic logic unit is disclosed herein which overcomes problems in the art discussed above. In accordance with the present invention, an ALU includes a plurality of individual programmable logic units which selectively implement arithmetic, logic, and equality comparison operations. One bit of each of two or more input signals is provided to respective ones of the logic units. One of a plurality of function signals, each of which being set equal to the truth table for a particular arithmetic, logic, or equality operation, is selectably provided to each of the logic units. Each of the logic units multiplexes the function signal provided thereto according to the particular bits of the input signals received therein to generate first and second output signals. These first and second output signals provided by each of the logic units are combined in an adder such that the resulting bit pattern represents the selected arithmetic, logic, or equality operation of the two or more input signals.

Abstract: A structure and a method allows I/O or memory addresses of hardware registers to be emulated in software by a central processing unit (CPU). In one embodiment, a first-in-first-out (FIFO) memory is provided to queue read and write operations of the emulated hardware registers. A programmable interrupt mask registers enables certain write operations to the emulated hardware registers to cause an interrupt at the CPU.

Abstract: A signed multiplier circuit which performs selectable multiplication operations on a first word having an upper byte and a lower byte and a second word having an upper byte and a lower byte. A first multiplier means generates a first product representative of the product of the upper bytes of the first and second words and the product of the lower bytes of the first and second words. A second multiplier means generates a second product representative of the product of the upper byte of the first word and the lower byte of the second word plus the product of the lower byte of the first word and the upper byte of the second word. The second multiplier means can be selectively disabled. When the second multiplier means is enabled, the multiplier circuit multiplies the first and second words. When the second multiplier means is disabled, the multiplier circuit multiplies the upper bytes of the first and second words and the lower bytes of the first and second words.

Abstract: A system and method for fast context switching between tasks by tracking task utilization of shared system resources and optimizing swapping the shared system resources to backing store by computing the difference between the current task's utilization of the system resources and the incoming task's utilization of the shared system resources and only swapping to backing store the difference between the current task's utilization, the available system resources, and the incoming task's needs.

Abstract: In accordance with the present invention, an adder is disclosed which combines byte boundary control signals with propagate-generate signal pairs immediately resulting from bit pairs of the input signals. Combining the byte boundary control signals with the first level propagate-generate signal pairs, rather than combining the byte boundary control signals with propagate-generate signal pairs indicative of the carry-out of a byte, allows the adder to utilize a more efficient tree signal path topology in which multiple levels of circuitry may be eliminated, thereby resulting in a reduction in propagation delay.

Abstract: A method of approximating the pixel intensity values of a current block using the pixel intensity values of a search window, wherein the precision of the number of bits used to represent the pixel intensity values is reduced. The pixel intensity values of the pixels in the current block are averaged to determine a first average pixel intensity value. The pixel intensity values of the current block which have a pixel intensity value less than the first average pixel intensity value are averaged to determine a second average pixel intensity value. The pixel intensity values of the current block which have a pixel intensity value greater than the first average pixel intensity value are averaged to determine a third average pixel intensity value. The first, second and third average pixel intensity values are used to determine thresholded pixel intensity values for the current block pixels and the search window pixels, thereby creating a thresholded current block and a thresholded search window.

Abstract: In a sound (music) synthesis system, a transition between levels of a sound parameter (e.g. volume) is synthesized by fitting a cubic (third degree) spline function between two discontinuous parameter levels. This advantageously eliminates any sound artifacts (pops or clicks) which would otherwise be present due to abrupt changes in the parameter. The cubic spline is fitted (interpolated) to match both the parameter value and its derivative with respect to time at each of the adjacent parameter levels on either side of the transition. The transition thus is advantageously kept brief and in addition it is possible to deal with the situation when the parameter dynamically changes during the transition period, again without causing undesirable sound artifacts.

Abstract: A single dirty bit is maintained in a memory controller for each cache line of a cached memory system using a cache write-back policy. The dirty bit is set after each write access, is reset after each read access in which a cache miss occurs, and is left unchanged after all other memory accesses. The dirty bit is used to select a delay value for submitting a retry request packet after a cache miss occurred in a memory access. The delay value minimizes memory access time by allowing for a write-back operation only when necessary.

Abstract: A structure and method for using variable length instructions in an instruction register having a fixed word boundary. The instruction register accommodates a first word and a second word. The first word has a first base instruction and a first flexible instruction aligned with first and second predetermined positions, respectively, in the instruction register. The second word has a second base instruction and a second flexible instruction aligned with third and fourth predetermined positions, respectively, in the instruction register. The first and second base instructions and the first and second flexible instructions each have a fixed length. The first base instruction can (1) stand alone as an independent instruction, (2) be combined with the first flexible instruction to form a once-extended instruction, or (3) be combined with the first and second flexible instructions to form a twice-extended instruction.

Abstract: A multiplier circuit for use in a system which includes an arithmetic and logic unit (ALU). The multiplier circuit includes a carry save stage which receives a first data value and a second data value, and in response, creates a carry signal and a sum signal. The carry and sum signals are provided to input leads of the ALU. The ALU is used to add the carry and sum signals to create a third data value which is equal to the product of the first and second data values. In one embodiment, the input leads to the ALU are multiplexed. Thus, one input lead of the ALU receives either the carry signal or a signal from a first input node and the second input lead of the ALU receives either the sum signal or a signal from a second input node.

Abstract: A multiplier circuit which performs selectable multiplication operations on a first word having an upper byte and a lower byte and a second word having an upper byte and a lower byte. A first multiplier circuit generates a first product representative of the product of the upper bytes of the first and second words and the product of the lower bytes of the first and second words. A second multiplier circuit generates a second product representative of the product of the upper byte of the first word and the lower byte of the second word plus the product of the lower byte of the first word and the upper byte of the second word. The second multiplier circuit can be selectively disabled. When the second multiplier circuit is enabled, the multiplier circuit multiplies the first and second words. When the second multiplier circuit is disabled, the multiplier circuit multiplies the upper bytes of the first and second words and the lower bytes of the first and second words.