Abstract: A shifter circuit and method for simultaneously and independently shifting and reordering a plurality of data bytes. The shifter circuit includes first and second registers which each receive a plurality of data bytes. The first register is coupled to a plurality of first buses, with each of the first buses receiving a data byte from the first register. Similarly, the second register is coupled to a plurality of second buses, with each of the second buses receiving a data byte from the second register. A multiplicity of third buses are coupled to the first and second buses. A byte shifting multiplexer is coupled to each of the third buses. A plurality of bit shifting multiplexer are coupled to the byte shifting multiplexers, with each bit shifting multiplexer being coupled to a pair of byte shifting multiplexers. A control circuit is coupled to the byte shifting and bit shifting multiplexers. The control circuit provides for independent control of each of the byte shifting multiplexers.