Patents Assigned to Ciena
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Publication number: 20250168963Abstract: A module for use in a hardware platform for networking, computing, or storage includes a printed circuit board assembly having a primary side and a secondary side, wherein the primary side has greater vertical clearance than the secondary side; at least one component mounted on the secondary side, the at least one component being placed on the secondary side due to an increased complexity and component density on the printed circuit board assembly preventing its placement on the primary side; and a floating heatsink assembly disposed on the secondary side to dissipate heat from the at least one component, the floating heatsink assembly being biased against the at least one component by at least one resilient member arranged within a limited vertical space on the secondary side.Type: ApplicationFiled: January 22, 2025Publication date: May 22, 2025Applicant: Ciena CorporationInventors: Mitchell O'Leary, Victor Aldea, Kamran Rahmani, Trevor Meunier, Peter Ajersch, Terence Graham, Marc Leclair
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Systems and Methods for Tracking, Predicting, and Mitigating Advanced Persistent Threats in Networks
Publication number: 20250165984Abstract: Systems and methods for tracking, predicting, and mitigating Advanced Persistent Threat (APT) attacks in a network include obtaining data including virtual currency transactions that are potentially associated with malicious activity; de-anonymizing at least a portion of the virtual currency transactions to identify originating or receiving endpoints; analyzing the de-anonymized virtual currency transactions to determine a threat index for a subscribed entity, wherein the threat index indicates a likelihood of an APT; and one or more of i) notifying the subscribed entity of the likelihood of the APT based on the threat index or ii) triggering one or more mitigation actions in the network.Type: ApplicationFiled: January 16, 2025Publication date: May 22, 2025Applicant: Ciena CorporationInventors: Sachin Subhedar, Roger Michael Elbaz, Aung Htay -
Publication number: 20250167884Abstract: An Optical Time Domain Reflectometer (OTDR) includes a transmitter configured to transmit first OTDR pulses, at a first pulse period and at a wavelength ?, over a fiber under test; a receiver configured to receive signals from the fiber under test; and circuitry configured to set the first pulse period and to average measurements resulting from the received signals, wherein the OTDR is configured to operate with a second OTDR at another end of the fiber under test for a bidirectional OTDR measurement, wherein the second OTDR uses the same wavelength ? and transmits second OTDR pulses at a second pulse period, different from the first pulse period.Type: ApplicationFiled: November 21, 2023Publication date: May 22, 2025Applicant: Ciena CorporationInventors: Jean-Luc Archambault, Xuesong Deng, Song Cao, Kevan Peter Jones
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Publication number: 20250158623Abstract: Aspects of the subject disclosure may include, for example, a multiphase clock generator having a plurality of digital phase interpolators each configured to create a generated clock signal according to an applied digital code, wherein a first digital code applied to a first digital phase interpolator and a second digital code applied to a second digital phase interpolator are chosen in a less precise range such that a first generated clock signal output by the first digital phase interpolator is as close to an ideal phase separation from a second generated clock signal output by the second digital phase interpolator, and wherein additional codes are applied to other digital phase interpolators in a more precise range to create generated clock signals having a deviation from an ideal separation from the first generated clock signal or the second generated clock signal that is less than a linear resolution of the applied digital code. Other embodiments are disclosed.Type: ApplicationFiled: November 15, 2023Publication date: May 15, 2025Applicant: CIENA CORPORATIONInventors: Jacob Pike, Sadok Aouini, Naim Ben-Hamida
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Patent number: 12300595Abstract: An apparatus includes a plurality of layers arranged on top of one another and including at least one ground layer and a signal layer; a first set of signal pads and a second set of signal pads on the signal layer; and a slot formed in a portion of the at least one ground layer between the first set of signal pads and the second set of signal pads. The apparatus can include an optical assembly housed by the plurality of layers and connected to the first set of signal pads and the second set of signal pads. The optical assembly can include a micro Intradyne Coherent Receiver (?ICR), a Coherent Driver Modulator (CDM), or a Coherent Optical Subassembly (COSA).Type: GrantFiled: November 7, 2023Date of Patent: May 13, 2025Assignee: Ciena CorporationInventors: Ramin Deban, Jean-Frédéric Gagné
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Patent number: 12301267Abstract: Aspects of the subject disclosure may include, for example, identifying a modulation scheme for transmitting data from a transmitter to a receiver, identifying a plurality of symbols associated with the modulation scheme, determining that a transfer function of a filter that is applied at the transmitter imposes an interdependence amongst at least two symbols of the plurality of symbols, determining, based on the transfer function, a joint probability distribution of the plurality of symbols that reduces a signal power of at least one signal that is used to transmit the data subject to a constraint that an information rate associated with the at least one signal is greater than a threshold, and causing the data to be transmitted via the at least one signal from the transmitter to the receiver in accordance with the joint probability distribution. Other aspects are disclosed.Type: GrantFiled: June 30, 2023Date of Patent: May 13, 2025Assignee: CIENA CORPORATIONInventors: Ramin Babaee, Shahab Oveis Gharan, Martin Bouchard
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Patent number: 12301238Abstract: Aspects of the subject disclosure may include, for example, a frequency divider, comprising a plurality of delay devices arranged to receive input clocks and generate output clocks, wherein one or more of the delay devices comprises a first transconductance element configured to receive a first input and provide a first output, a second transconductance element configured to receive a second input and provide a second output, a first feedforward transconductance element that cross couples the first input and the second output, and a second feedforward transconductance element that cross couples the second input and the first output. Other embodiments are disclosed.Type: GrantFiled: November 8, 2023Date of Patent: May 13, 2025Assignee: CIENA CORPORATIONInventors: Mohammad Honarparvar, Ahmed Mustafa, Naim Ben-Hamida, Nahla Abouelkheir
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Publication number: 20250150065Abstract: Aspects of the subject disclosure may include, for example, a frequency divider, comprising a plurality of delay devices arranged to receive input clocks and generate output clocks, wherein one or more of the delay devices comprises a first transconductance element configured to receive a first input and provide a first output, a second transconductance element configured to receive a second input and provide a second output, a first feedforward transconductance element that cross couples the first input and the second output, and a second feedforward transconductance element that cross couples the second input and the first output. Other embodiments are disclosed.Type: ApplicationFiled: November 8, 2023Publication date: May 8, 2025Applicant: CIENA CORPORATIONInventors: Mohammad Honarparvar, Ahmed Mustafa, Naim Ben-Hamida, Nahla Abouelkheir
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Publication number: 20250150440Abstract: Systems and methods for protecting sensitive data in a system include receiving, by one or more processors, a data model comprising one or more data fields; identifying, within the data model, at least one field designated as sensitive data; automatically creating an encrypted form of the sensitive data at a framework level without requiring an application-level encryption process; and incorporating the encrypted form of the sensitive data into the data model in place of the unencrypted data.Type: ApplicationFiled: January 13, 2025Publication date: May 8, 2025Applicant: Ciena CorporationInventor: David Miedema
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Patent number: 12294348Abstract: A single stage electromagnetic interference (EMI) filter circuit includes a power source input configured to connect to a power source; an equivalent common mode and differential mode filter including a single inductor having both common mode inductance for common mode filtering and specific parasitic inductance; and a differential capacitance stage connected to the single inductor in parallel, wherein a combination of the specific parasitic inductance and capacitance of the differential capacitance stage are used to provide differential mode filtering.Type: GrantFiled: April 6, 2023Date of Patent: May 6, 2025Assignee: Ciena CorporationInventors: Karan Goel, Chander Gupta, Sujoy Mandal, Anand Kumar
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Patent number: 12294639Abstract: A packet processing module includes circuitry configured to receive feedback signals from each of N first-in, first-out (FIFOs), N is an integer that is greater than or equal to 1, determine a clock speed for the packet processing module based on the received feedback signals, and program a phase lock loop (PLL) based on the determined clock speed where the PLL provides a module clock at the determined clock speed to a packet processing circuit which is configured to receive and process packets from the N FIFOs. The feedback signals are a deterministic representation of processing needed for the packet processing circuit given a current state of packets available.Type: GrantFiled: December 18, 2023Date of Patent: May 6, 2025Assignee: Ciena CorporationInventor: Kenneth Edward Neudorf
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Publication number: 20250141785Abstract: A network element includes a plurality of ports including a first set of ports configured to connect to a router via a Link Aggregation and a second set of ports configured to communicatively connect to another network element via 1+1 protection over a Time Division Multiplexing (TDM) network; and circuitry interconnecting the plurality of ports and configured to perform a first bridge and select function to convert the Link Aggregation protection associated with the first set of ports to a single connection, and perform a second bridge and select function to convert the single connection to the 1+1 protection associated with the second set of ports. The first bridge and select function and the second bridge and select function are each configured to close one type of protection and open another type of protection.Type: ApplicationFiled: December 11, 2023Publication date: May 1, 2025Applicant: Ciena CorporationInventors: Alexander Young, Rajagopalan Kannan, Kalp Desai, Chandrasekhar Viswanathan, Matthew Yuen, Sitaram Patro, Matthew Danby Jemmeson
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METHODS, SYSTEMS, AND DEVICES FOR PROVISIONING AND IMPLEMENTING AN INTELLIGENT EDGE LINK ON A ROUTER
Publication number: 20250141795Abstract: Aspects of the subject disclosure may include, for example, provisioning the router with a first application, and provisioning the router with a first intelligent edge link associated with the first application within a network operating system. The first application is separate from the network operating system. Further embodiments include mapping the first intelligent edge link to a first virtual interface associated with the first application. The first virtual interface is within the first application separate from the network operating system. Other embodiments are disclosed.Type: ApplicationFiled: October 31, 2023Publication date: May 1, 2025Applicant: CIENA CORPORATIONInventors: David H. Gilson, Wade Aaron Miller, Sai Madhavi Vadlamudi, Padma Sanampudi, Praveen Kumaar Kejriwal -
Publication number: 20250141731Abstract: Aspects of the subject disclosure may include, for example, obtaining data regarding a plurality of fault management services in a network, wherein the plurality of fault management services respectively correspond to a plurality of fault management sessions, and wherein the data identifies priority information for at least one fault management session of the plurality of fault management sessions, and performing one or more actions relating to the plurality of fault management sessions in accordance with the priority information. Other embodiments are disclosed.Type: ApplicationFiled: December 12, 2023Publication date: May 1, 2025Applicant: CIENA CORPORATIONInventors: Priyanshu Lnu, Ashutosh Aggarwal
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Patent number: 12287511Abstract: An integrated circuit can include one or more photonic layers that include a plurality of photonic integrated circuit portions. A first optical coupler is configured to couple an optical mode of an optical wave to a first photonic integrated circuit portion in the one or more photonic layers. A second optical coupler is configured to couple an optical mode of an optical wave to a second photonic integrated circuit portion that is optically uncoupled to the first photonic integrated circuit portion. The second photonic integrated circuit portion comprises a polarization-sensitive photonic component, and an optical splitter comprising at least one input port optically coupled to the polarization-sensitive photonic component and at least two output ports including a first output port and a second output port.Type: GrantFiled: May 24, 2022Date of Patent: April 29, 2025Assignee: Ciena CorporationInventors: Marie-Josee Picard, Christine Latrasse
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Patent number: 12289343Abstract: Systems and methods for monitoring a network slice are provided. A method, according to one implementation, include extracting information from network traffic received from one or more User Plane Function (UPF) components of a network slice; examining the extracted information using Machine Learning (ML), and, in response to detecting of one or more malicious threats based on the examined extracted information by the ML, causing one or more actions to isolate the network traffic to protect at least the network slice from the one or more malicious threats.Type: GrantFiled: June 13, 2022Date of Patent: April 29, 2025Assignee: Ciena CorporationInventors: Petar Djukic, David Jordan Krauss, James P'ford't Carnes, III, William Kaufmann, Balaji Subramaniam
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Patent number: 12289391Abstract: Aspects of the subject disclosure may include, for example, a device including a phase rotator configured to receive a read clock, a flip flop configured to obtain an incoming data stream, and a controller. The controller may be configured to control the phase rotator to perform phase rotation of the read clock based on information-carrying level transitions in the incoming data stream, cause a gapped read clock and an inversion of the gapped read clock to be derived in accordance with the phase rotation, where the gapped read clock being derived via gapping operations associated with the read clock, and output clock selection signals that enable the flip flop to selectively sample the incoming data stream using the gapped read clock and the inversion, thereby facilitating a data handoff between asynchronous clock domains. Other embodiments are disclosed.Type: GrantFiled: September 7, 2022Date of Patent: April 29, 2025Assignee: CIENA CORPORATIONInventors: Andrew McCarthy, Sadok Aouini, Manoj Verghese, Naim Ben-Hamida
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Patent number: 12288954Abstract: A module for use in a hardware platform for networking, computing, and/or storage includes a printed circuit board assembly having a primary side and a secondary side, wherein the primary side includes more physical space, in a vertical direction extending out from the printed circuit board assembly, than the secondary side; electrical and/or optical components disposed on the primary side of the printed circuit board assembly; and a secondary side heatsink located on and extending from the secondary side, wherein the secondary side heatsink is disposed to one of i) an electrical and/or optical component disposed on the secondary side, and ii) an optical component disposed on the primary side, for thermal management.Type: GrantFiled: September 9, 2020Date of Patent: April 29, 2025Assignee: Ciena CorporationInventors: Mitchell O'Leary, Victor Aldea, Kamran Rahmani, Trevor Meunier, Peter Ajersch, Terence Graham, Marc Leclair
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Publication number: 20250133013Abstract: Systems and methods for segment compaction in Segment Routing with resiliency to restoration include, responsive to a path having been computed in a Segment Routing network from a source node to a destination node, assuming all failed links in the Segment Routing network are temporarily restored; and determining a segment list, with all of the failed links assumed temporarily restored, that corresponds to the computed path, such as by preferring node segments over adjacency segments to match the computed path.Type: ApplicationFiled: October 18, 2023Publication date: April 24, 2025Applicant: Ciena CorporationInventors: Todd Defilippi, Cengiz Alaettinoglu
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Publication number: 20250130095Abstract: Aspects of the subject disclosure may include, for example, deriving substantially orthogonal optical fields from an output of an optical source, implementing a delay on one of the substantially orthogonal optical fields, resulting in time delayed optical fields, performing coherent detection of the time-delayed optical fields, resolving electrical field signals based on the coherent detection, and causing the electrical field signals to be processed so as to estimate a property of the optical source, wherein estimation of the property facilitates disturbance detection and localization. Other embodiments are disclosed.Type: ApplicationFiled: October 20, 2023Publication date: April 24, 2025Applicant: CIENA CORPORATIONInventors: Mohammad Ebrahim Mousa Pasandi, Maurice O'Sullivan, Michael Reimer, Yixiang Hu, David V. Plant, Ramon Gutierrez-Castrejon