Patents Assigned to Cirrus Logic, Inc.
  • Patent number: 11335338
    Abstract: A speech recognition system comprises: an input, for receiving an input signal from at least one microphone; a first buffer, for storing the input signal; a noise reduction block, for receiving the input signal and generating a noise reduced input signal; a speech recognition engine, for receiving either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block; and a selection circuit for directing either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block to the speech recognition engine.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 17, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: John Paul Lesso, Robert James Hatfield
  • Patent number: 11337010
    Abstract: The present disclosure describes techniques for altering the epoxy wettability of a surface of a MEMS device. Particularly applicable to flip-chip bonding arrangements in which a top surface of a MEMS device is adhered to a package substrate. A barrier region is provided on a top surface of the MEMs device, laterally outside a region which forms, or overlies, the backplate and/or the cavity in the transducer substrate. The barrier region comprises a plurality of discontinuities, e.g. dimples, which inhibit the flow of epoxy.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: May 17, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Marek Sebastian Piechocinski, Roberto Brioschi, Rkia Achehboune
  • Patent number: 11329620
    Abstract: A method for calibrating gain in a multi-path subsystem having a first processing path, a second processing path, and a mixed signal return path, may include low-pass filtering an input signal and a mixed signal return path signal generated from the input signal at subsonic frequencies to generate a filtered input signal and a filtered mixed signal return path signal and tracking and correcting for a gain difference between the first processing path and the second processing path based on the filtered input signal and the filtered mixed signal return path signal.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: May 10, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Johann G. Gaboriau, David M. Olivenbaum, Xiaofan Fei, Amar Vellanki, Venugopal Choukinishi, Gautham Sivasankar, Wai-Shun Shum
  • Patent number: 11322157
    Abstract: A method of speaker authentication comprises: receiving a speech signal; dividing the speech signal into segments; and, following each segment, obtaining an authentication score based on said segment and previously received segments, wherein the authentication score represents a probability that the speech signal comes from a specific registered speaker. In response to an authentication request, an authentication result is output based on the authentication score.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: May 3, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Carlos Vaquero Avilés-Casco, David Martínez González, Ryan Roberts
  • Patent number: 11322465
    Abstract: A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 3, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Kathryn R. Holland, Marc L. Tarabbia, Yaoyu Pang, Alexander Barr
  • Patent number: 11323810
    Abstract: A microphone system, comprises a first transducer, for generating a first acoustic signal, and a second transducer, for generating a second acoustic signal. A high-pass filter receives the first signal and generates a first filtered signal, and a low-pass filter receives the second signal and generates a second filtered signal. An adder forms an output signal of the microphone system as a sum of the first filtered signal and the second filtered signal.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: May 3, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: John P. Lesso, Thomas I. Harvey
  • Patent number: 11323804
    Abstract: An apparatus of reducing feedback noise in an acoustic system, the apparatus comprising: a first input for receiving a first signal derived from a first microphone associated with a first channel, the first signal comprising a first set of frequency sub-bands; a second input for receiving a second signal derived from a second microphone associated with a second channel, the second signal comprising second set of frequency sub-bands, the first and second sets of frequency sub-bands having matching frequency ranges, each frequency sub-band of the first and second sets of frequency sub-bands having a frequency of greater than a threshold frequency; and one or more processors configured to: determining feedback at a first speaker associated with the first channel; and responsive to determining feedback, mix each of the first set of frequency sub-bands with a corresponding one of the second set of frequency sub-bands to generate a mixed output signal comprising a mixed set of frequency sub-bands; wherein the mixin
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: May 3, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Henry Chen, Tom Harvey, Brenton Steele
  • Patent number: 11322131
    Abstract: Embodiments generally relate to a signal processing device for on ear detection for a headset. The device comprises a first microphone input for receiving a microphone signal from a first microphone, the first microphone being configured to be positioned inside an ear of a user when the user is wearing the headset; a second microphone input for receiving a microphone signal from a second microphone, the second microphone being configured to be positioned outside the ear of the user when the user is wearing the headset; and a processor.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 3, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: Brenton Steele
  • Patent number: 11316508
    Abstract: A system may include an output driving stage comprising a first switch configured to selectively open and close an electrical path between a first supply voltage and an output terminal of the output driving stage and a second switch configured to selectively open and close an electrical path between a second supply voltage and the output terminal of the output driving stage, wherein the second supply voltage is lower than the first supply voltage. The system may also include detection and protection circuitry configured to monitor a physical quantity indicative of the second supply voltage and responsive to the physical quantity exceeding an overvoltage threshold, electrically isolate the output terminal from the second supply voltage.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: April 26, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Ramin Zanbaghi, Cory J. Peterson
  • Patent number: 11315543
    Abstract: A system performs pole-zero or IIR modeling and estimation of an inter-microphone transfer function between first and second microphones that output respective first and second microphone signals. The system includes a first adaptive FIR filter to which the first microphone signal is provided, a delay element that delays the second microphone signal by a predetermined delay amount, and a second adaptive FIR filter to which the delayed second microphone signal is provided. A first coefficient of the second adaptive FIR filter is constrained to a fixed non-zero value. The filters are jointly adapted to minimize an error signal that is a difference of the two filters outputs. The delay is small: approximately the acoustic propagation delay between the two microphones and is not determined by the environmental reverberation characteristics. The error signal may serve as a noise reference in a noise canceller, for implementing far-field beamforming with low delay.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: April 26, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Khosrow Lashkari, Narayan Kovvali, Seth Suppappola
  • Patent number: 11317227
    Abstract: Monitoring circuitry, comprising: a current monitoring unit operable to monitor a speaker current flowing through a speaker and generate a monitor signal indicative of that current; and a controller operable, based on a control signal, to control the current monitoring unit to control whether the monitor signal is generated and/or a property of the monitor signal.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 26, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John P. Lesso
  • Patent number: 11316523
    Abstract: A system may include a digitally-controlled oscillator configured to generate an output clock signal based on a control signal received at an input of the digitally-controlled oscillator and a control circuit configured to calculate an error signal between the output clock signal and an external reference clock signal, filter the error signal to generate a correction signal, generate the control signal based on the correction signal, and switch between a first mode of operation and a second mode of operation without artifacts on the correction signal during switching between the first mode and the second mode.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: April 26, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Saurabh Singh, Jaimin Mehta, Sriram Balasubramanian, Anindya Bhattacharya
  • Patent number: 11303294
    Abstract: The present disclosure provides digital to analog conversion circuitry comprising: a set of input nodes for receiving a digital input code; an output node for outputting an analog output signal representative of the input code; and a plurality of selectable conversion elements, wherein a parameter of each of the plurality of selectable conversion elements is configured such that a transfer function between the input code and the output analog signal is non-monotonic.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: April 12, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: Gavin McVeigh
  • Patent number: 11300987
    Abstract: A system may include an integrated circuit comprising an on-chip power supply and an internal power rail, a gate-controlled supply switch configured to be coupled between the on-chip power supply and an external power supply such that the internal power rail is regulated by the on-chip power supply when the gate-controlled supply switch is open and the internal power rail is regulated by the external power supply when the gate-controlled supply switch is closed, and a control circuit configured to monitor conditions associated with the on-chip power supply when the gate-controlled supply switch is transitioning between switch states and based on the conditions, control a rate of charging or discharging of a capacitance coupled to a gate of the gate-controlled supply switch.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 12, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Kathryn R. Holland, Wesley L. Mokry, Neel Pramanik, Christian Larsen
  • Patent number: 11299392
    Abstract: The Application describes a substrate design for a MEMS transducer package. The substrate is defined by a conductive layer which forms the upper and lower surfaces of the substrate. The substrate is also provided with a conductive portion which is electrically isolated from the rest of the conductive layer. The conductive portion is supported between a first plane defined by the upper surface of the substrate and a second plane defined by the lower surface of the substrate by an electrically insulating moulding substance.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 12, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Rkia Achehboune, Roberto Brioschi, Dimitris Drogoudis, David Patten
  • Patent number: 11296598
    Abstract: Driver circuitry for driving a load based on an input signal, comprising: at least one variable boost stage comprising: first and second input nodes configured to receive a first voltage and a second voltage respectively; first and second flying capacitor nodes for connection to a flying capacitor therebetween; a network of switching paths for selectively connecting the first and second input nodes with the first and second flying capacitor nodes; an output stage for selectively connecting a driver output node to each of the first and second flying capacitor nodes; and a controller operable in a first boost mode to: control the output stage to selectively connect the driver output node to the first flying capacitor node; control the network of switching paths to switch connection of the second flying capacitor node between the first and second input nodes at a controlled duty cycle; and in a first charge top-up cycle, control the network of switching paths to connect the first input node to the first flying c
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: April 5, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Eric J. King, Axel Thomsen, Anthony S. Doy, Thomas H. Hoff, John L. Melanson
  • Patent number: 11296666
    Abstract: A high CMRR current monitoring circuit includes a first stage that receives a current sense signal, a voltage across a current sense resistor in series with an output of a class-D amplifier. First stage is powered by at least one floating supply and/or reference that tracks the amplifier output. First stage applies gain to the current sense signal to generate an intermediate signal. A second stage receives the intermediate signal and is powered by a ground-referenced supply and provides an amplified representation of the current sense signal. The floating supply is supplied by a capacitive-coupled power source driven by the ground-referenced supply. The second stage output may be a voltage relative to ground or a digital signal. The intermediate signal may be a current, digital signal, or amplified version of the current sense signal voltage. The first stage may be a transconductance amplifier and the second stage a transimpedance amplifier.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 5, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Christian Larsen, John L. Melanson
  • Patent number: 11296663
    Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a first sense resistor coupled between the first low-side switch and the ground voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first low-side switch is activated.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: April 5, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Ramin Zanbaghi, Cory J. Peterson, Anand Ilango, Eric Kimball
  • Patent number: 11296685
    Abstract: A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: April 5, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Ramin Zanbaghi, Anuradha Parsi, Kyehyung Lee, John L. Melanson
  • Patent number: 11288193
    Abstract: A system for atomically transferring vectors of data from a transmitter of the vectors of data to a receiver of the vectors of data may include a plurality of memory buffers configured to store the vectors of the data, each buffer configured to store one vector of the vectors of data at a time, the plurality of memory buffers comprising at least three memory buffers and a controller for controlling the plurality of memory buffers. The controller may be configured to, responsive to a condition for transferring information represented by the vectors of data to the receiver, determine which of the plurality of buffers from which the receiver may receive most-recently updated information completely written to the plurality of buffers by the transmitter.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: March 29, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Nathan Daniel Pozniak Buchanan, Nariankadu D. Hemkumar, Sachin Deo