Patents Assigned to Cirrus Logic, Inc.
  • Patent number: 11515707
    Abstract: A power delivery system may include a power converter configured to electrically couple to a power source and further configured to supply electrical energy to one or more loads electrically coupled to an output of the power converter, and control circuitry configured to select a constraint factor from a plurality of different constraint factors based on at least one of an input voltage to the power converter and a power level available to the power converter, and control the power converter in accordance with the constraint factor.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: November 29, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Graeme G. Mackay, Ajit Sharma, Jason W. Lawrence, Eric J. King
  • Patent number: 11507199
    Abstract: A system may include a resistive-inductive-capacitive sensor, a driver configured to drive the resistive-inductive-capacitive sensor with a plurality of driving signals, each driving signal of the plurality of driving signals having a respective driving frequency, and a measurement circuit communicatively coupled to the resistive-inductive-capacitive sensor and configured to measure a first value of a physical quantity associated with the resistive-inductive-capacitive sensor in response to a first driving signal of the plurality of driving signals, wherein the first driving signal has a first driving frequency; measure a second value of the physical quantity associated with the resistive-inductive-capacitive sensor in response to a second driving signal of the plurality of driving signals, wherein the second driving signal has a second driving frequency; measure a third value of the physical quantity associated with the resistive-inductive-capacitive sensor in response to the first driving signal; measure a
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: November 22, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John L. Melanson
  • Patent number: 11509272
    Abstract: This application describes time-encoding modulator circuitry (200), and in particular a PWM modulator suitable for use for a class-D amplifier. A forward signal path receives a digital input signal (Din) and outputs an output PWM signal (Sout) and includes a first PWM modulator (101). A feedback path provides feedback to an input of the first PWM modulator (101). The feedback path includes an ADC (203) which receive a first PWM signal (Sa) derived from the output PWM signal. The ADC (203) includes a second PWM modulator (401) which generates a second PWM signal (Sb) based on the first PWM signal. A controller (201) controls the second PWM modulator such that a PWM carrier of the second PWM signal is phase and frequency matched to a PWM carrier of the output PWM signal.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: November 22, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: John P. Lesso, Toru Ido
  • Patent number: 11509292
    Abstract: A method for identifying a mechanical impedance of an electromagnetic load may include generating a waveform signal for driving an electromagnetic load and, during driving of the electromagnetic load by the waveform signal or a signal derived therefrom, receiving a current signal representative of a current associated with the electromagnetic load and a back electromotive force signal representative of a back electromotive force associated with the electromagnetic load. The method may also include implementing an adaptive filter to identify parameters of the mechanical impedance of the electromagnetic load, wherein an input of a coefficient control for adapting coefficients of the adaptive filter is a first signal derived from the back electromotive force signal and a target of the coefficient control for adapting coefficients of the adaptive filter is a second signal derived from the current signal.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 22, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Emmanuel Marchais, Pablo Peso Parada, Eric Lindemann
  • Patent number: 11507267
    Abstract: A force sensing system for determining if a user input has occurred, the system comprising: an input channel, to receive an input from at least one force sensor; an activity detection stage, to monitor an activity level of the input from the at least one force sensor and, responsive to an activity level which may be indicative of a user input being reached, to generate an indication that an activity has occurred at the force sensor; and an event detection stage to receive said indication, and to determine if a user input has occurred based on the received input from the at least one force sensor.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: November 22, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Hamid Sepehr, Pablo Peso Parada, Willem Zwart, Tom Birchall, Michael Allen Kost, Tejasvi Das, Siddharth Maru, Matthew Beardsworth, Bruce E. Duewer
  • Patent number: 11508379
    Abstract: Voice biometrics scoring is performed on received asynchronous audio outputs from microphones distributed at ad hoc locations to generate confidence scores that indicate a likelihood of an enrolled user speech utterance in the output, a subset of the outputs is selected based on the confidence scores, and the subset is spatially processed to provide audio output for voice application use. Alternatively, asynchronous spatially processed audio outputs and corresponding biometric identifiers are received from corresponding devices distributed at ad hoc locations, audio frames of the outputs are synchronized using the biometric identifiers, and the synchronized frames are coherently combined. Alternatively, uttered speech associated with respective ad hoc distributed devices is received and non-coherently combined to generate a final output of uttered speech.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: November 22, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Samuel P. Ebenezer, Ghassan Maalouli
  • Patent number: 11500469
    Abstract: An integrated haptic system may include a digital signal processor and an amplifier communicatively coupled to the digital signal processor and integrated with the digital signal processor into the integrated haptic system. The digital signal processor may be configured to receive a force sensor signal indicative of a force applied to a force sensor and generate a haptic playback signal responsive to the force. The amplifier may be configured to amplify the haptic playback signal and drive a vibrational actuator communicatively coupled to the amplifier with the haptic playback signal as amplified by the amplifier.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: November 15, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Harsha Rao, Rong Hu, Carl Lennart Ståhl, Jie Su, Vadim Konradi, Teemu Ramo, Anthony Stephen Doy
  • Patent number: 11501092
    Abstract: This application relates to computing circuitry, and in particular to analogue computing circuitry suitable for neuromorphic computing. An analogue computation unit for processing data is supplied with a first voltage from a voltage regulator which is operable in a sequence of phases to cyclically regulate the first voltage. A controller is configured to control operation of the voltage regulator and/or the analogue computation unit, such that the analogue computation unit processes data during a plurality of compute periods that avoid times at which the voltage regulator undergoes a phase transition which is one of a predefined set of phase transitions between defined phases in said sequence of phases. This avoids performing computation operations during a phase transition of the voltage regulator that could result in a transient or disturbance in the first voltage, which could adversely affect the computing.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: November 15, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John Paul Lesso
  • Patent number: 11500404
    Abstract: The present disclosure relates to circuitry for selecting a bias voltage to output at a bias voltage output node of the circuitry. The circuitry comprises a first circuit node configured to receive a first voltage from a first, unregulated, voltage source and a second circuit node configured to receive a second voltage from a second, regulated, voltage source. A switch arrangement configured to selectively couple the bias voltage output node to the first circuit node or the second circuit node is also provided.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: November 15, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: John B. Bowlerwell, Andrew J. Howlett, Graeme S. Angus, Andrei Dumitriu
  • Patent number: 11500405
    Abstract: The present disclosure relates to voltage regulator circuitry. The voltage regulator circuitry comprises an output device configured to provide a regulated output voltage and a controllable shunt device configured to provide a current path from the output device for a shunt current. The shunt current is variable according to a control signal supplied to the controllable shunt device.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: November 15, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John A. Breslin
  • Patent number: 11502671
    Abstract: A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: November 15, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Qiang Li, Rahul Singh, Paul Astrachan, Kyehyung Lee
  • Patent number: 11489498
    Abstract: An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: November 1, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Chandra Prakash, Cory J. Peterson, Eric Kimball
  • Patent number: 11488606
    Abstract: An audio system receives an audio signal from a digital microphone, which has an analog-digital converter with a controllable sampling rate. In response to a determination that a predetermined trigger phrase is not detected in the decimated audio signal, the sampling rate of the analog-digital converter in the digital microphone is controlled such that the audio signal has a first sample rate. In response to a determination that the predetermined trigger phrase is detected in the decimated signal, the sampling rate of the analog-digital converter in the digital microphone is controlled such that the audio signal has a second sample rate higher than the first sample rate, and the audio signal is applied to a spoof detection circuit, to determine whether the received signal contains live speech or replayed speech.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: November 1, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John P. Lesso
  • Patent number: 11487861
    Abstract: Embodiments of the disclosure provide a mechanism for performing a biometric algorithm on ear biometric data acquired from a user. The mechanism may be used for biometric authentication, or in-ear detect, for example. In one embodiment, a method is provided in which a quality metric of an input signal to a transducer and/or a signal on a return path from the transducer is monitored. One or more steps of a biometric process, comprising monitoring of a parameter related to an admittance of the transducer, comparison of the parameter to a stored profile for an authorised user, generation of a score based on the comparison, comparison of the score to one or more threshold values, and initiation of one or more actions, may be performed responsive to the quality metric meeting one or more criteria.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: November 1, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John Paul Lesso
  • Patent number: 11489606
    Abstract: Calibration of devices communicating on a shared data bus may improve data integrity on the shared data bus by reducing duty cycle distortion. Duty cycle distortion may be reduced by adjusting timing of a transceiver in a device for communicating on the shared data bus using calibration codes. The calibration codes may be loaded into memory and used to reconfigure the transceiver timing on the shared data bus with reconfiguration occurring within one or more unit-intervals of time. The calibration code may be used, for example, to adjust a PMOS or NMOS trim circuit at the transceiver.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: November 1, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Anthony Louviere, John L. Melanson, Gabriel Vogel
  • Patent number: 11488583
    Abstract: A method of own voice detection is provided for a user of a device. A first signal is detected, representing air-conducted speech using a first microphone of the device. A second signal is detected, representing bone-conducted speech using a bone-conduction sensor of the device. The first signal is filtered to obtain a component of the first signal at a speech articulation rate, and the second signal is filtered to obtain a component of the second signal at the speech articulation rate. The component of the first signal at the speech articulation rate and the component of the second signal at the speech articulation rate are compared, and it is determined that the speech has not been generated by the user of the device, if a difference between the component of the first signal at the speech articulation rate and the component of the second signal at the speech articulation rate exceeds a threshold value.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 1, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John Paul Lesso
  • Patent number: 11489505
    Abstract: A method of equalising an audio signal derived from a microphone, the method comprising: receiving the audio signal; applying an order-statistic filter to the audio signal in the frequency domain to generate a statistically filtered audio signal; equalising the received audio signal based on the statistically filtered audio signal to generate an equalised audio signal.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: November 1, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: John P. Lesso, Craig Alexander Anderson
  • Patent number: 11490198
    Abstract: A method for detecting wind noise incident on a single microphone may include receiving an audio signal indicative of sound incident on the single microphone, dividing the audio signal into a plurality of audio frames, and determining whether wind noise is incident on the single microphone based on a combination of a correlation metric between successive audio frames of the plurality of audio frames and a power ratio difference between a first power ratio and a second power ratio. The first power ratio may equal an amount of power present in a first frequency range of the audio signal to a total amount of power present in the audio signal across all frequencies. The second power ratio may equal an amount of power present in a second frequency range of the audio signal to the total amount of power present in the audio signal across all frequencies.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: November 1, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Ning Li, Teja Buddha, Mohamed Sabet, Doug Olsen
  • Patent number: 11489534
    Abstract: Digital-to-analog converter (DAC) architecture, comprising: a matrix DAC array comprising a plurality of cells arranged in a first dimension and a second dimension, each cell comprising a local decoder configured to transition the cell between at least two states; and decoding circuitry configured to: receive a digital input signal; and control the plurality of local decoders based on a received digital input signal, wherein each incremental change in the digital input signal results in a transition of a single cell of the plurality of cells such that the plurality of cells transition in sequence, the sequence of transitions of the plurality of cells defining a path through the DAC array; wherein when the path proceeds in the first dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time; and wherein when the path proceeds in the second dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: November 1, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Seung Bae Lee, Sunny Bhagia, Jaiminkumar Mehta, Anindya Bhattacharya, John L. Melanson
  • Patent number: 11483654
    Abstract: This application relates to driver circuitry (200) for receiving a digital input signal (D) and outputting, at first and second output nodes (203p, 203n), first and second analogue driving signals respectively for driving a transducer (101), e.g. loudspeaker, in a bridge-tied-load configuration. The driver circuitry may particularly be suitable for driving low-impedance transducers. The driver circuitry has first and second digital-to-analogue converters (201p, 201n) configured to receive the digital input signal and the outputs of the first and second digital-to-analogue converters are coupled to the first and second output nodes respectively. A differential-output amplifier circuit (202) has outputs connected to the first and second output nodes and is configured to regulate the outputs of the digital-to-analogue converters at output nodes to provide the analogue driving signals.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: October 25, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Andrew J. Howlett, Sharjeel Riaz, John P. Lesso