Abstract: A method and apparatus for synchronizing a local clock value in a wireless receiver receiving a data unit containing synchronization information. The method includes receiving a first data unit containing synchronization information, extracting the synchronization information from the received first data unit, copying a local free-running clock at a known reference point in time relative to the time the first data unit was received to generate a local timestamp; and calculating an offset to the free-running clock using the extracted synchronization information and the local timestamp, the calculating in non real-time, such that the sum of the calculated offset and the value of the free-running clock provides a local clock value that is approximately synchronized in time. The apparatus implementing the method is part of a node of a wireless station, and provides a time synchronization function, typically at the MAC layer.

Abstract: A digital AGC system for burst operation, particularly suited for receiving packets in a wireless local area network. One embodiment includes a log detector that provides a signal strength measure, called the received signal strength indication (RSSI) over a wide dynamic range. The AGC system includes estimating the power in a received signal by averaging the log of the signal power. The Start of Packet detection avoids using the radio receiver's main analog to digital converters to preserve power.

Abstract: A monolithic transceiver integrated circuit that includes a substrate, a transmitter subsystem of one or more subcircuits on the substrate, and a receiver subsystem of one or more subcircuits on the substrate. Also included is a bias current supply coupled to the receiver and transmitter subsystems to provide bias current. The bias current supply includes a first bias circuit on the substrate coupled to, and to supply bias current to, a first subcircuit of the transmitter subsystem. The first bias circuit includes a first current modulator having a first switch input to indicate that the bias current is to start or stop being supplied to the first subcircuit. The first current modulator is to control the rate of change of supplied bias current in response to the first switch input. The first subcircuit may be a power amplifier. The control of the rate of change reduces oscillator pull in at least one oscillator included in the integrated circuit.

Abstract: The present invention relates to systems and methods for processing and transmitting data that preserves the timing relationship of the data being transmitted and/or processed. In one embodiment, the present invention uses a timestamp. The timestamp stores the timing relationship of data in the bitstream as it appeared before any processing that may alter the timing relationship of the data. The data may then be processed. By storing the original timing relationship of data, before any processing that alters the timing relationship of data, the present invention allows for the recreation of the original timing relationship between data. Thus, any jitter introduced by processing the data may be removed or substantially reduced.

Abstract: A method and apparatus for efficient implementation and evaluation of state machines and programmable finite state automata is described. In one embodiment, a state machine architecture comprises a plurality of node elements, wherein each of the plurality of node elements represents a node of a control flow graph. The state machine architecture also comprises a plurality of interconnections to connect node elements, a plurality of state transition connectivity control logic to enable and disable connections within the plurality of interconnections to form the control flow graph with the plurality of node elements, and a plurality of state transition evaluation logic coupled to the interconnections and operable to evaluate input data against criteria, the plurality of state transition evaluation logic to control one or more state transitions between node elements in the control flow graph.

Abstract: A monolithic radio integrated circuit includes a substrate, a set of one or more analog subcircuits on the substrate, a programmable bias current supply on the substrate coupled to the set to provide bias currents to the analog subcircuits of the set including programmable bias currents to one or more analog subcircuits forming a first subset of the set, and a digital subsection coupled to the programmable bias supply to determine the bias currents supplied to the analog subcircuits of the first subset, such that one or more characteristics of the radio integrated circuit are modifiable by programming the programmable bias supply.

Abstract: A wireless local area network system comprises a 5.0+ GHz radio transceiver with two receiving antennas and one transmitting antenna. A transmitter power amplifier output is connected to the transmitting antenna through a 6–8 pole filter to control spurious signal output. Each receiving antenna is fitted with its own low-noise amplifier followed by a simple bandpass filter. Each bandpass filter feeds a diversity switch with a single output to a single receiver. The radio system constitutes a physical-layer (PHY) part of a wireless local-area network.

Abstract: A novel and useful mechanism for detecting the nodes connected to a network device and for creating a ring network from the nodes detected thereby. The invention simplifies insertion, removal and modification of nodes in the ring by detecting and reconfiguring the ring without requiring intervention by a user. Identification information messages generated by network devices and sent out on all links and received over a plurality of ports are used in identifying and determining the connectivity and topology of the network devices. The resulting topology information is stored in a node database. The contents of the node database are then used to generate one or more ring networks, wherein each ring generated corresponds to a unique line speed. The connectivity of the one or more rings generated is stored in a ring database and the rings configured therefrom.

Abstract: Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.

Abstract: A radio receiver for implementing the physical layer receiving function (PHY) of a wireless data network includes a receive processing pipeline for processing samples of a received packet of data. The samples enter the receive processing pipeline at a first sample rate. A counter generates a running count indicative of the number of samples that have entered the processing pipeline. A comparison unit coupled to the counter determines from the running count if all the samples of the received packet have entered the pipeline. An output of the comparison unit indicates whether or not all samples have entered the pipeline. A clock unit coupled to the comparison unit output provides a clock signal to the pipeline, causing the processing pipeline to process the samples entering the pipeline at a first rate compatible with the first sample rate until the comparison unit output indicates that all samples have entered the pipeline.

Abstract: A wireless computer data network includes several untethered mobile units that make ad-hoc data connections with an Internet-connected base station using the IEEE-802.11a standard. Each unit includes a radio transceiver fully integrated on a single semiconductor chip. The receiver portion is a double-conversion superheterodyne type, and shares the same intermediate and local oscillator frequencies with a two-stage up-conversion transmitter. Two on-chip synthesizers that each include a voltage-controlled oscillator and phase-locked loop can be operated independently for each conversion stage, or operated in offset mode. External reference frequencies can be injected for voltage-controlled oscillator and phase-locked loop testing, chip characterization, and automatic compensation modeling. Each mobile and base unit can be outfitted with transmit/receive antenna transfer switches, RF-power amplifiers, and low-noise receiver amplifiers to increase operating range.

Abstract: A MAC controller for a station in a wireless network, and a method for transmitting packets according to a wireless network MAC protocol. A MAC controller includes a packet scheduler connected to an interface for providing packets for transmission, and transmit hardware connected to a physical layer interface of the station to execute sub-sequences. The transmit hardware includes a buffer to receive from the scheduler and store a set of execution data, and also a signal path to the scheduling engine to provide an indication to the packet scheduler of the outcome of a sub-sequence. The transmit hardware is connected to a receiver to indicate the reception at the wireless station of a data unit that may be a response to a transmission of a sub-sequence.

Abstract: A configurable Viterbi decoder to decode a coded signal for inclusion in a radio receiver for implementing the physical layer receiving function (PHY) of a wireless data network. The decoder includes a branch metric generator with an input to the coded signal, an ACS subsystem coupled to the branch metric generator, and a survivor memory unit coupled to the ACS subsystem. The decoder includes a plurality of outputs each providing a decoded version of the input signal decoded to a distinct decision depth such that the Viterbi decoder is programmable to decode the signal to one of a plurality of decision depths.

Abstract: Devices, software and methods are provided for encoding voice data to conceal packet loss. In addition to regular encoding, an abbreviated portion of the frame is encoded, and transmitted redundantly afterwards. Optionally the redundant encoding is in relation to an attribute of the sound represented by the data. The attribute of the sound can be pitch information, peak information, or bandwidth information.

Abstract: A system and method are disclosed for using standard issue synchronous optical network (SONET) framers to comply with current automatic protection system (APS) standards. Each standard framer includes its own section, line, and path layer termination. The working set of lines and protection set of lines of the APS system are switched after the path layer rather than before. A firmware solution allows for a proper use of various error indication signals.

Abstract: Devices, software and methods are provided for generating aggregate comfort noise for teleconferencing over IP networks. A transcoding component includes a decoder for decoding streams of packets. A summing component has a summer with summing inputs to receive the decoded streams of packets. The summing component has at least one silence flag input, and an additional signaling path is used by the transcoding component to signal to the silence flag input if any of the decoded streams of packets includes a silence identification packet. In another embodiment, the summing component may or may not include the silence flag input, but the device includes an aggregate comfort noise generation component. The aggregate comfort noise may be programmed to be a balanced representation of all background noises.

Abstract: The present invention discloses a method and system for synchronizing processing modules. More specifically the present invention utilizes a master clock signal and associated synchronization information to coordinate the function dictated by packets within a synchronization stream. The master clock has multiple sources. Each module in the system is connected to each clock source to ensure that if one source fails, the module will not fail. The clock signal to each module is further passed through a locked oscillator, which will continue to maintain the clock signal should the master clock signal fail. Each module contains a sync decoder to decode the SYNC packets in the synchronization stream, into system time events. The system time events are then passed to a plurality of event receivers. Each event receiver contains at least one flywheeling counter to ensure that each event receiver remains in synchronization with the system time events being passed by the sync decoder.

Abstract: A phase locked loop (PLL) frequency synthesizer to produce a local oscillator signal for a superheterodyne transmitter for operation at a first and a second RF frequency band that are disparate. The transmitter has a fixed intermediate frequency that is a sizable fraction of the bandwidth of one or more of the RF bands. The superheterodyne transmitter includes a first and a second RF upconverter, each having a local oscillator input coupled to the frequency synthesizer. The synthesizer includes a voltage controlled oscillator (VCO) to provide a VCO frequency signal and a non-integer frequency multiplier to produce a frequency multiplied signal having a frequency wither at the VCO frequency or at a non-integer multiple of the VCO signal depending on a control input.

Abstract: The present invention extends the generalized Lloyd algorithm (GLA) for vector quantizer (VQ) codebook improvement and codebook design to a new linearly-constrained generalized Lloyd algorithm (LCGLA). The LCGLA improves the quality of VQ codebooks, by forming the codebooks from linear combinations of a reduced set of base codevectors. The present invention enables a principled approach for compressing texture images in formats compatible with various industry standards. New, more flexible compressed texture image formats are also made possible with the present invention. The present invention enhances signal compression by improving traditional VQ approaches through the integrated application of linear constraints on the multiple pattern and signal prototypes that represent a single pattern or block of signal samples.

Abstract: This invention discloses an intra-frame complexity based dynamic GOP system and method for the encoding of MPEG-2 video streams. The present invention may be used as a rate control tool to improve video quality. The selective insertion of low complexity I frames in scene changes such as fades is disclosed. It is disclosed that the selective use of I frames in certain scene change situations can improve encoder performance, particularly when encoding at a low bit rate.