Patents Assigned to Clear Logic, Inc.
  • Patent number: 5949323
    Abstract: A radiant-energy configurable fuse structure and array are provided in which the fuse body of the fuse is wider than the fuse connection terminals. The fuse body can be circular or polygonal to capture more of the radiant energy from a targeting beam, which reduces the energy required to blow the fuse. As a result, unrelated circuit elements and patterned lines can be placed closer together in a laser fuse array, thereby increasing the packing density of such arrays.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: September 7, 1999
    Assignee: Clear Logic, Inc.
    Inventors: Alan H. Huggins, Ron Thomas, David E. Schmulian
  • Patent number: 5945238
    Abstract: A method is provided for making re-usable configuration masks by initially patterning a mask blank using precision mask-making tools. The mask is then covered with an opaque material, and desired configuration points for a particular ASIC are selected with a non-precision laser. After the particular configuration pattern is no longer needed, the remaining opaque material is removed. The mask can then be re-configured for a new design by covering the mask with a new layer of opaque material and selecting new configuration points. Such a mask reduces both time and costs for creating a set of mask designs because a single mask can be re-used for several different designs without the further need of precision mask-making tools.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: August 31, 1999
    Assignee: Clear Logic, Inc.
    Inventors: Alan H. Huggins, John MacPherson, Richard J. Schmidley
  • Patent number: 5885749
    Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning a photoresist layer on an insulative layer with a standard via precision mask to define all possible vias, and 2) using a targeting energy beam to select the desired via locations, which are then etched and interconnections made, for customization or repair of the integrated circuit. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: March 23, 1999
    Assignee: Clear Logic, Inc.
    Inventors: Alan H. Huggins, John MacPherson
  • Patent number: 5840627
    Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with standard precision masking techniques to define all possible connections, vias or cut-points, and 2) using a non-precision targeting energy beam to select the desired connections, vias or cut-points for customization. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: November 24, 1998
    Assignee: Clear Logic, Inc.
    Inventor: Alan H. Huggins