Abstract: The present disclosure relates to a multiplier, a multiply-accumulate circuit, an operational circuit, a processor, and a calculation apparatus. The operational circuit includes an input processing circuit and the multiply-accumulate circuit. The input processing circuit receives a first number and outputs the first number as a first multiplicator for feeding into the multiply accumulate circuit by negating a sign bit of the first number in a case in which the first number is a signed number, and directly outputs the first number as the first multiplicator for feeding into the multiply-accumulate circuit in a case in which the first number is an unsigned number. The input processing circuit further receives a previously known second number and directly outputs the second number as a second multiplicator for feeding into the multiply-accumulate circuit. The multiply-accumulate circuit includes a multiplication subcircuit and an accumulation subcircuit.

Abstract: A barrier bollard includes a warning device, a light source, and a barrier body arranged on a main body to be movable via a drive over a barrier height between an open and a barrier position. The light source is arranged on a lateral surface of the barrier body over a warning height in a warning region associated with an upper side of the barrier body. The light source emits an optical warning signal in an activated state. The upper side is substantially flush with the surface of the main body in the open position. In the barrier position, the upper side is moved out from the ground to project in the barrier height over the main body. The barrier body is movable for a warning sequence in a warning position where it is partially moved out from the main body and is temporarily stationary for a warning time.

Abstract: A module motor is provided, including a base, a holder, a driver assembly, and a housing. The housing is formed with an accommodation cavity having an opening. The holder and the driver assembly are disposed in the accommodation cavity, the driver assembly is connected between the holder and the base, and the driver assembly is configured to drive the holder to move relative to the base in a direction perpendicular to the base. The housing is provided with a stop structure, the stop structure includes a connection part and a first stop part, the connection part and the first stop part are of an injection-molding integrated structure, the connection part is embedded in a through hole, and the first stop part extends into the accommodation cavity. A hardness of the stop structure is greater than or equal to a shore hardness of 20.

Abstract: A method for processing audio data includes: obtaining audio data, and obtaining a key frame of the audio data by performing keyword detection on the audio data; determining a second speech application based on the key frame, and sending a frame identifier of the key frame to the second speech application; and extracting first audio data from the audio data according to the key frame, and sending the first audio data to the second speech application for speech recognition.

Abstract: A dust core includes a metal magnetic powder and a binding agent that binds particles of the metal magnetic powder. The binding agent includes a silicone resin and an epoxy resin. In an elemental analysis of the dust core based on an image of a cross section of the dust core, when a silicon (Si) element and a carbon (C) element are detected on a weight basis at 15 measurement points between the particles of the metal magnetic powder in the image, a difference between a maximum value and a minimum value of x/(x+y) values at the 15 measurement points is at most 0.243, where x denotes an amount of the Si element detected and y denotes an amount of the C element detected.

Abstract: A coil component comprises a first wire including a winding portion wound around a winding core portion of a core, a first end portion electrically connected to a terminal electrode provided in a first flange portion, and a first extended portion connecting the winding portion and the first end portion. In a first direction, the first end portion is positioned on a first side with respect to a central axis of the winding core portion, and a first boundary portion which is a boundary portion between the first extended portion and the winding portion is positioned on a second side with respect to the central axis. A corner of the winding core portion is positioned between the first boundary portion and the first end portion in a circumferential direction. A gap is interposed between the first extended portion and the corner.

Abstract: A power converter including a power semiconductor module and a power semiconductor module, and a method of manufacturing the same comprising an insulating substrate for a heat dissipation substrate, a heat dissipation substrate for a power semiconductor module, a power semiconductor module including a heat dissipation substrate. A heat dissipation substrate for a power semiconductor module may include a first metal plate, an insulating substrate bonded to the first metal plate, and a second metal plate bonded to the insulating substrate. A first thickness of the first metal plate may be different from the second thickness of the second metal plate. The first thickness of the first metal plate may be thinner than the second thickness of the second metal plate. The first metal plate may comprise a circuit pattern electrically connected to a power semiconductor device, and the second metal plate may include a marked unique code.

Abstract: There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.

Abstract: Examples of the present disclosure provide packet forwarding methods, a network device and a storage medium. In the examples of the present disclosure, the automation of deploying SRv6 in a layer three network is achieved by automatically allocating different locators to the gateway device and different APs connected to the gateway device, so as to fully utilize the advantages brought by SRv6 in the layer three network. Further, in this example, an SRv6 tunnel is deployed between the gateway device and the AP based on locators allocated to the gateway device and the AP, and the packet is transmitted between the gateway device and the AP through the SRv6 tunnel, thus achieving the packet forwarding method applied to the layer three network with SRv6 deployed.

Abstract: A light-emitting module according to an embodiment comprises: a substrate; a plurality of light-emitting diode chips which are disposed on the substrate; a plurality of wavelength converters which are disposed on the plurality of light-emitting diode chips respectively; and a white wall which surrounds the plurality of light-emitting diode chips and the plurality of wavelength converters, wherein each of the plurality of wavelength converters includes a side surface which is inclined at an inclination angle of 80 degrees or less to the upper surface of the wavelength converter.

Abstract: A furopyrazine derivative that is a novel organic compound is provided. The organic compound has a furopyrazine skeleton and is represented by General Formula (G1). In General Formula (G1), Q represents oxygen or sulfur, Ar1 represents a substituted or unsubstituted condensed aromatic ring, R1 and R2 independently represent hydrogen or a group having 1 to 100 total carbon atoms, and at least one of R1 and R2 has a hole-transport skeleton.

Abstract: The present invention relates to the technical field of medicines and disclosed are a neuroprotective polypeptide compound and an application thereof. The neuroprotective polypeptide compound comprises a polypeptide having the following chemical formula and a salt thereof: (M)m-(Lys-Leu-Ser-Ser-Ile-Glu/Asp-Ser/Thr-Asp/Glu-Val/Leu)-(N)n; m and n are integers from 0 to 3, but m and n are not zero at the same time; M is beta-Ala-His, beta-Ala-1-Methyl-His or beta-Ala-3-Methyl-His, and N is beta-Ala-His, beta-Ala-1-Methyl-His or beta-Ala-3-Methyl-His. An intravenous dosage of only 3 mg/kg can unexpectedly achieve a significant therapeutic effect and achieve the same effect as NA1. The polypeptide compound can be used in combination with a hemolytic drug to provide a new possibility for the treatment of stroke.

Abstract: A connector assembly includes a printed circuit board having a first electrical pin and a second electrical pin positioned on the printed circuit board, a socket connector including an insulation housing having a first socket and a second socket, and a locker movable between a first position and a second position. The first electrical pin is removably inserted into the first socket and the second electrical pin is removably inserted into the second socket. The insulation housing has a locking cavity communicated with the first socket. The locker engages with the first electrical pin to lock the first electrical pin in the first socket in the first position, and the locker disengages from the first electrical pin to release the locking of the first electrical pin in the second position.

Abstract: A display panel has functional component regions arranged along a first direction and a display region at least partially surrounding the functional component regions. The functional component regions include a first functional component region and a second functional component region. The display panel includes first signal lines located in the display region. One of the first signal lines has a least one part extending in the first direction, and the first signal lines are arranged in a second direction intersecting with the first direction. The first signal lines include a first-type signal line and a second-type signal line, and the first-type signal line includes at least two first-type connecting line. The second-type signal line includes a second-type connecting line.

Abstract: A processor-implemented method with image generation includes obtaining a first image, determining predicted texture information of a target image corresponding to the first image through a texture prediction model, based on the first image, determining predicted color information of the target image through a color prediction model, based on the first image, and generating the target image based on the first image, using the predicted texture information and the predicted color information, wherein a format of the target image is different from that of the first image.

Abstract: A passing determination device acquires a first captured image obtained by repeatedly capturing an image of a region including a passing determination position of a trailer from a front of the trailer in a traveling direction of the trailer, and detects the trailer from the first captured image. Further, the passing determination device includes a processor configured to determine that the trailer detected from the first captured image captured at a first time passes through the passing determination position when the trailer is detected from the first captured image captured at the first time and the trailer is not detected from the first captured image captured within a first time period from the first time.

Abstract: A multilayer electronic component according to an example embodiment of the present disclosure may include: a body including a dielectric layer and internal electrodes alternately disposed with the dielectric layer in a first direction, and including first and second surfaces opposing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction; side margin portions disposed on the fifth and sixth surfaces; and external electrodes disposed on the third and fourth surfaces, and an additional pattern spaced apart from the internal electrodes may be disposed in at least one of a region between the internal electrodes and the fifth surface or a region between the internal electrodes and the sixth surface.

Abstract: A multilayer electronic component may include: a body including a dielectric layer and internal electrodes alternately disposed with the dielectric layer; an interface plating layer disposed on an end of the internal electrode; and an external electrode disposed to contact at least a portion of an end of the dielectric layer disposed between the internal electrodes and to cover the interface plating layer, and including a conductive resin layer including a conductive metal and a resin.

Abstract: A method of fabricating a semiconductor device includes forming a dielectric layer on a lower structure. The method includes forming an opening to penetrate through the dielectric layer. The method includes alternately repeating a first operation, in which a first sputtering deposition process is performed to form a first metal pattern in the opening, and a second operation, in which a second sputtering deposition process is performed to form a second metal pattern in the opening, two or more times to form a first metal layer. The method includes forming a second metal layer on the first metal layer in an electroplating manner, and planarizing the first and second metal layers. Moreover, first and second process times, during which the first sputtering deposition process and the second sputtering deposition process, respectively, are performed, are each about five seconds or less.

Abstract: A semiconductor package may include a chip stack, a first semiconductor chip provided on a top surface of the chip stack, outer terminals provided on a bottom surface of the chip stack, and a mold layer provided on a bottom surface of the first semiconductor chip to enclose the chip stack. The chip stack may include a second semiconductor chip including first penetration vias, which are provided in second semiconductor chip and are exposed to an outside of the second semiconductor chip. The chip stack may include third semiconductor chips stacked on a top surface of the second semiconductor chip. Each of the third semiconductor chips may include second penetration vias, which are provided to penetrate the same and are exposed to an outside of the same. The first semiconductor chip may have a width larger than the chip stack, and the first semiconductor chip may include a logic chip.