Abstract: Provided are a thin-film transistor substrate that has enhanced electrical characteristics, such as off-current characteristics of a thin-film transistor, without increasing the number of mask processes, a display apparatus, and a method of manufacturing the thin-film transistor substrate. The thin-film transistor substrate includes: a semiconductor layer including a first conductive region, a second conductive region, and a first semiconductor region; a lower electrode disposed on the semiconductor layer and at least partially overlapping the first semiconductor region; and an upper electrode disposed on the lower electrode and at least partially overlapping the first semiconductor region, a first boundary between the first semiconductor region and the first conductive region coincides with an edge of the upper electrode, and a second boundary between the first semiconductor region and the second conductive region coincides with an edge of the lower electrode or an edge of the upper electrode.

Abstract: A pump assembly is provided with a coupling unit that connects a pump casing to a motor casing. The coupling unit has a pump-side connection part and a motor-side connection part. An annular element is arranged between the connection parts using supports which minimize heat transfer between the pump-side connection part and the motor-side connection part.

Abstract: A scan driver includes a first transistor including gate, first, and second electrodes coupled to a Q node, a scan clock line, and a scan line. A second transistor includes gate and first electrodes coupled to a scan carry line, and a second electrode coupled to the Q node. A third transistor includes gate and first electrodes coupled to a first control line and a sensing carry line. A fourth transistor includes a gate and first electrode coupled to the sensing carry line and the third transistor first electrode. A fifth transistor includes gate, first, and second electrodes coupled to a fourth transistor second electrode, a second control line, and a node. A capacitor includes first and second electrodes coupled to the fifth transistor first and gate electrodes. A sixth transistor includes gate, first, and second electrodes coupled to a third control line, the node, and the Q node.

Abstract: In an intermediate region surrounding a periphery of an active region, a gate polysilicon wiring layer is provided on a gate insulating film at a front surface of a semiconductor substrate, via a field oxide film. An inner end portion of the gate polysilicon wiring layer faces a p-type region of a surface region at the front surface of the semiconductor substrate, via only the gate insulating film. In the intermediate region, at corners thereof facing corners of the active region, a low carrier lifetime region containing a carrier lifetime killer is provided so as to overlap the p-regions and, in a depth direction, face the gate polysilicon wiring layer, whereby the lifetime of the minority carriers of the corner portions of the intermediate region is shorter than the lifetime of the minority carriers of linear portions of the intermediate region.

Abstract: A display device and a method of manufacturing the same are provided. The display device includes a pixel including an emission area and a non-emission area, a transistor of the pixel, a protective layer on the transistor, and including an opening area overlapping the non-emission area, alignment electrodes on the protective layer and spaced apart from each other, light emitting elements between respective ones of the alignment electrodes in the emission area, and a connection electrode electrically connected to the light emitting elements, and electrically connected to the transistor in the opening area.

Abstract: An electronic pen cartridge is replaceable with a refill of a stationery ballpoint pen such that the stationery ballpoint pen housing can be reused as the electronic pen housing. The electronic pen cartridge is of a capacitance type and includes a pen tip which is projectable from an opening on one side in an axial direction of the pen housing. Inside the tubular cartridge housing are an electronic circuit including a signal transmission circuit configured to generate a signal to be supplied to a position detection sensor, and a rechargeable power storage device configured to supply a power supply voltage to the electronic circuit. A coil is wound around a portion of the cartridge housing, the portion located at a position where there is room in the pen housing. The power storage device is charged by a current induced in the coil based on an externally supplied magnetic field.

Abstract: The invention relates to a pump arrangement (1) with at least one temperature-controllable housing part, wherein at least one temperature-controllable housing part (3) comprises a first wall (27) that is in contact with the temperature-controllable medium and a second wall (28) that is at a distance from the first wall (27). The first wall (27) and the second wall (28) form a temperature control chamber (29).

Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A transistor is formed in a first region on a first side of a single crystalline silicon substrate. A step layer is formed in a second region on the first side of the single crystalline silicon substrate. A channel structure extending through a stack structure and in contact with the step layer is formed. The stack structure includes interleaved dielectric layers and conductive layers on the step layer. Part of the single crystalline silicon substrate that is in the second region is removed from a second side opposite to the first side of the single crystalline silicon substrate to expose the step layer from the second side.