Abstract: A method for coating chips resting, by a rear face opposite to a front face, on a main face of a support substrate, and separated from each other by an inter-chip space, includes a step of forming a photosensitive coating film covering the front faces and the inter-chip spaces. The method further includes a first photolithographic sequence which comprises an insolation sub-step, and a dissolution sub-step. The sequence leads to a partial removal of the photosensitive coating film so as to maintain the film exclusively at the inter-chip spaces and, advantageously recessed relative to the front faces.

Abstract: A method for manufacturing a single crystal may be by solution growth from a seed crystal, in a unit including a tank and a growth platform having a lower plate. The method may include: fastening the seed to the lower plate; introducing a crystallization solution of density dS into the tank; treating the solution in order to render it supersaturated; bringing the seed into contact with the supersaturated solution; rotating the platform until the single crystal is obtained. Before bringing the seed into contact with the supersaturated solution, the method may include forming, in the tank, of a zone for trapping parasitic crystals of density dC by introducing, into the tank, a liquid, immiscible with the growth solution, of density d>dS and d<dc, which forms with the growth solution an interface located below the lower plate.

Abstract: An electronic device for storing, controlling and manipulating electron or hole spin based semiconductor qubits, the device including an electrically insulating layer and on a front face of the insulating layer, a trapping structure for electrons or holes which includes: a channel portion including at least one layer portion of semiconductor material, as well as a plurality of gates distributed for trapping at least one electron or hole in the channel portion, and on the back side of the insulating layer, an electrical track extending parallel to the insulating layer, for generating an oscillating magnetic field acting on the at least one electron or hole trapped in the trapping structure.

Abstract: An imaging device (100) configured to image a sample (102), comprising: a light source (104) emitting a light; a light deflection device configured to deflect the light emitted by the light source towards the sample, comprising a material portion (106) provided with a first main face (108) arranged opposite the sample (102), a second main face (110), and a first lateral face (112) towards which the light is emitted by the light source; an imager (118) having a detection face (122) arranged opposite the second main face and intended to receive the light backscattered by the sample; wherein one amongst the main faces is provided with oblique portions (114) each configured to deflect a portion of the received light towards the sample (102), and with planar portions (116) configured to let the light backscattered by the sample pass, and wherein each pixel (120) of the imager (118) is arranged opposite one of the planar portions (116) of said one amongst the first and second main faces (108, 110).

Abstract: A method for producing an individualization zone of a microelectronic chip having a first and a second electrical track level and an interconnection level including vias, includes providing the first level and a dielectric layer, forming an etching mask on the dielectric layer, randomly depositing particles on the etching mask, and forming a lithographic layer having opening patterns. The mask layer is etched through opening patterns to form mask openings, then the dielectric layer is etched through the mask openings, so as to obtain functional via openings and degraded via openings. The via openings are filled so as to form the vias of the interconnection level, the vias including functional vias at the functional openings and malfunctional vias at the degraded openings.

Abstract: A method for manufacturing a phase change stack having a crystallographic structure made of layers separated by van der Waals pseudo-gaps, may include: providing a substrate; forming the stack on the substrate, including (i) forming the first layer, and (ii) forming the second layer on the first layer. Advantageously, after formation of the stack, at least one curing annealing is carried out. The curing annealing may be such that the stack has, after annealing, a nominal defect rate less than at least 50% of an initial defect rate of the stack.

Abstract: A computer platform includes an artificial neural network (ANN) as well as a classifier. The ANN is configured, after a learning phase, to transform an input data vector into a discriminating feature vector having a smaller dimension. A user then generates, from a plurality of reference data vectors, the same plurality of reference feature vectors, which are encrypted in an encryption module using the public key of a homomorphic cryptosystem and stored in a reference database of the platform. When the user requests the classification of an input data vector, the ANN, or a copy thereof, provides the classifier with a corresponding discriminating feature vector (y). Distances from the vector to the different reference feature vectors are calculated in the homomorphic domain and the index of the reference feature vector closest to y, i.e. the identifier i0 of the class to which it belongs, is returned to the user.

Abstract: A method for determining the thermal donor concentration of a test sample made of a semiconductor material, includes providing a reference sample made of the same semiconductor material and having a known thermal donor concentration; measuring a photoluminescence signal of the reference sample for a photon energy comprised between 0.65 eV and 0.8 eV, the photoluminescence signal of the reference sample exhibiting an intensity peak in a photon energy range of 0.65 eV to 0.8 eV; determining, from the photoluminescence signal, an experimental relationship between the thermal donor concentration and a parameter representative of the intensity peak; measuring a photoluminescence signal of the test sample for at least one photon energy comprised between 0.65 eV and 0.8 eV; determining from the photoluminescence signal a specific value of the parameter; and determining the thermal donor concentration from the specific value of the parameter by using the experimental relationship.

Abstract: A photodiode including a detection portion made of a first germanium-based crystalline semiconductor material, including a first doped region, a second doped region, and an intermediate region; an interposed portion, in contact with the first doped region, made of a crystalline semiconductor material having a natural lattice parameter equal, to within 1%, to a natural lattice parameter of the first semiconductor material, and a bandgap energy at least 0.5 eV higher than that of the first semiconductor material.

Abstract: An interconnector for solar cell strings intended to form a photovoltaic module, the interconnector comprising at least one cell interconnecting strip extending beyond a cell located at the end of the string through an end, and at least one string interconnecting strip, a section of one from among the cell interconnecting strip and the string interconnecting strip has a substantially constant surface, and a variable shape between a first zone of a first thickness and a second zone of a second thickness, the second thickness being strictly less than the first thickness and the second thickness being strictly less than 50 ?m. Each second zone thus constitutes a resistance welding zone without loss in terms of conduction. Without extra thickness at the interconnections, the risk of the module breaking is limited.

Abstract: A method for forming a doped zone of a transistor includes providing a stack having at least one active layer made from a semiconductor material, and a transistor gate pattern having at least one lateral side, and modifying a portion of the active layer so as to form a modified portion made of a modified semiconductor material. The modified portion extends down to the at least one lateral side of the gate pattern, at the edge of a non-modified portion above which the gate pattern is located. The method also includes forming a spacer on the lateral side, removing the modified portion by selective etching of the modified semiconductor material with respect to the semiconductor material of the non-modified portion, so as to expose an edge of the non-modified portion, and forming the doped zone by epitaxy starting from the exposed edge.

Abstract: A voltage divider circuit includes at least two FDSOI transistors (TP1, TP2) of a first type connected to a first supply potential and arranged in a current mirror structure, two FDSOI transistors (TN1, TN2) of a second type and an electrical load (R), the drain of a first—respectively second—transistor (TN1) of the second type being connected to the drain of a first—respectively second—transistor (TP1) of the first type, the drain of the first transistor of the second type being connected to the front-face gate of this same transistor, the front-face gates of the first and second transistors of the second type being connected to one another, the source of the first transistor of the second type being connected to a second supply potential and the load being placed between the source of the second transistor of the second type and the second supply potential.

Abstract: A method of performing magnetic resonance imaging of a body includes a) immerging the body in a static and substantially uniform magnetic field; b) exciting nuclear spins inside the body using at least one radio-frequency pulse; c) applying to the body a time-varying magnetic field gradient defining at least one trajectory (ST) in k-space and simultaneously acquiring samples of a magnetic resonance signal so as to perform a pseudo-random sampling (KS) of the k-space; and d) applying a sparsity-promoting nonlinear reconstruction algorithm for reconstructing a magnetic resonance image of the body; wherein, at least in a low-spatial frequency region of the k-space, the distance between any two adjacent points belonging to a same trajectory is lower than 1/FOV, FOV being the size of a field of view of the reconstructed image. A magnetic resonance imaging apparatus for carrying out such a method is also provided.

Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.

Abstract: A method for forming a Bragg reflector includes after forming first trenches in the stack, which are intended to form structures of the distributed Bragg reflector, forming a sacrificial interlayer at least in the first trenches, depositing a second masking layer at least inside the first trenches, forming second trenches intended to form sidewalls of the laser, removing the second masking layer from inside the first trenches, removing said sacrificial interlayer so as to remove, by lift-off, residues of the second masking layer that remain inside the first trenches, and filling said first trenches with at least one metal material.

Abstract: A resistive memory cell may be provided with a first electrode and a second electrode arranged on either side of a dielectric layer and facing an interface between a first region and a second region, The first and second region may have different compositions in terms of doping and/or dielectric constant, so as to confine the zone of reversible creation of a conductive filament at the interface.

Abstract: A method for producing an individualization zone of a microelectronic chip having a first and a second electrical track level, and an interconnection level comprising vias, includes providing the first level and a dielectric layer, forming an etching mask having openings on the dielectric layer, and randomly depositing particles in the openings, by deposition then recirculating the particles on the surface of the etching mask. The dielectric layer is etched through mask openings, so as to obtain functional via openings and degraded via openings. The via openings are filled so as to form the vias of the interconnection level, the vias including functional vias at the functional openings and malfunctional vias at the degraded openings.

Abstract: An integration system and method for the manufacture of radio frequency transmission front-end modules with radio frequency integrated circuit(s) and self-biased magnetic component(s) integrated on a “Wafer Level Packaging”-type technology. This integration makes it possible to design efficient, compact and low-cost front-end modules.

Abstract: A method for crystallising an amorphous layer included in a stack, extending directly in contact with a crystalline layer of the stack by forming an interface with the crystalline layer, and having a first face opposite the interface, and having a melting threshold EM corresponding to the energy density to be provided to the amorphous layer to achieve its melting, for a thickness Ep of the amorphous layer defined between the first face and the interface, the method including a crystallisation annealing of the amorphous layer by subjecting it, by zones, to laser pulses, and in each zone, the laser pulses are emitted by series, each laser pulse having an energy density EDi different from one series to another so as to maintain the energy density of the pulses of each series below the melting threshold.

Abstract: The present description concerns an electronic device comprising: a silicon layer, an insulating layer in contact with a first surface of the silicon layer, a transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the device further comprising, under the gate portion, a partial insulating trench in the silicon layer extending from a second surface of the silicon layer down to a depth smaller than the thickness of the silicon layer.