Abstract: The invention relates to aA process for producing conductive connections to an electronic chip, comprising the following steps: a) depositing an insulating layer on one face of a wafer; b) producing a layer based on at least one metal covering the insulating layer and equipped with first apertures; c) etching second apertures in the insulating layer in the extension of the first apertures by plasma etching in a plasma based on at least one halogen-containing compound; d) vacuum annealing the entire structure obtained after step c); and e) forming, after step d), the conductive connections in the second apertures.

Abstract: A device including: a paper film including cellulose fibers, a first surface, and a second surface opposite to the first surface; and at least one first heat-sensitive resistor having a negative temperature coefficient, the first heat-sensitive resistor including a first electrode arranged on the first surface, a second electrode arranged on the second surface, the first and second electrodes having at least first portions facing each other, the first heat-sensitive resistor further including the portion of the paper film arranged between the first portions facing each other. The invention also relates to a method of manufacturing such a device.

Abstract: An AC/DC conversion circuit, including: four bidirectional switches forming an H bridge; a capacitor connected between input nodes of the bridge; a capacitor connected between output nodes of the bridge; and a control circuit capable of controlling the bridge alternately to a first configuration where first and second diagonals of the bridge are respectively conductive and non-conductive, and to a second configuration where the first and second diagonals are respectively non-conductive and conductive, the control circuit being capable, during a phase of transition between the first and second configurations, of: turning off the switches of the first diagonal; and for each switch of the second diagonal, turning on the switch only when the voltage thereacross takes a zero value.

Abstract: A CMOS pixel including: a photodiode having a terminal connected to a potential GND and another terminal connected to a sense node by a first MOS transistor; a second MOS transistor connecting the sense node to a potential VDDH; and a third MOS transistor having its gate connected to the sense node, the transistors having a same gate insulator thickness, wherein the third transistor has a gate length and/or width smaller than those of the first and second transistors, wherein difference VDDH-GND is greater than the nominal voltage of the third MOS transistor, and wherein the body or drain region of the third transistor is connected to a potential VL between potentials VDDH and GND.

Abstract: A process for fabricating an electronic device including a substrate and microwires or nanowires resting on the substrate, the process including successive steps of covering the wires with an insulating layer, covering the insulating layer with an opaque layer, depositing a first photoresist layer over the substrate between the wires, etching the first photoresist layer over a first thickness by photolithography, etching the first photoresist layer remaining after the preceding step over a second thickness by plasma etching, etching the portion of the opaque layer not covered by the first photoresist layer remaining after the preceding step, etching the portion of the insulating layer not covered by the opaque layer, removing the first photoresist layer remaining after the preceding step, and removing the opaque layer.

Abstract: A voltage selection circuit, including: first and second nodes of application of first and second input voltages; a third output voltage supply node; first and second MOS transistors respectively coupling the first and third nodes and the second and third nodes; and a control circuit capable of keeping the first and second transistors either respectively on and off or respectively off and on, the control circuit including a feedback loop from the third node to the gate of the first transistor and being capable, during a transition phase, of controlling the first transistor in linear operating region to apply a DC voltage ramp to the third node.

Abstract: A memory slot including a pad formed of a stack of regions made of thin layers, including a first region made of a nonmagnetic conducting material; a second region made of a magnetic material exhibiting a magnetization in a direction perpendicular to the principal plane of the pad; a third region made of a nonmagnetic conducting material of different characteristics to those of the first region; the pad resting on a conducting track adapted to cause the flow of a programming current of chosen sense, in which the pad has an asymmetric shape with respect to any plane perpendicular to the plane of the layers and parallel to the central axis of the track, and with respect to its barycenter.

Abstract: An optoelectronic device including a carrier having a face including flat butt-jointed facets inclined in relation to each other; seeds, mainly made of a first compound selected from the group including the compounds III-V, the compounds II-VI, and the compounds IV, in contact with the carrier in the region of at least some of the joints between the facets; and conical or frustoconical, wire-like three-dimensional semiconductor elements of a nanometric or micrometric size, mainly made of the first compound, on the seeds.

Abstract: An electronic device having at least a first portion including a metal oxide that is in contact with a second portion including the said metal oxide, the first portion being semiconducting and the second portion being electrically insulating.

Abstract: An X-ray detector including a substrate having opposite first and second faces, at least a first temperature sensor on the side of the first or second face, and at least one stack including of a copper oxide layer and a copper layer. The copper oxide layer is located between the copper layer and the substrate. The stack covers at least partially the first temperature sensor or is at least partially opposite the first temperature sensor.

Abstract: A register including: a plurality of volatile memory cells each having a first input and an output, the volatile memory cells being coupled in series with each other via their first inputs and outputs; a non-volatile memory comprising a plurality of non-volatile memory cells; and one or more serial connections adapted to perform at least one of: serially supply data to be written to the non-volatile memory from a last or another of the volatile memory cells to the non-volatile memory during a back-up operation of data stored by the volatile memory cells; and serially supply data read from the non-volatile memory to a first of the volatile memory cells during a restoration operation of the data stored by the volatile memory cells.

Abstract: A retroreflective screen including a first film having a surface including a plurality of microrecesses, each microrecess having a bottom substantially parallel to the mean plane of the screen and first and second lateral walls substantially orthogonal to each other and substantially orthogonal to the bottom, the first and second lateral walls and the bottom of the microrecess joining at a same point and forming a trihedron.

Abstract: An optoelectronic device provided with a support including a face having at least one concave or convex portion, the amplitude of the sagitta of said portion being higher than 1/20th of the chord of the portion, and light-emitting diodes arranged on the portion, each light-emitting diode including a cylindrical, conical or frustoconical semiconductor element in contact with the portion, the amplitude of the sagitta of the contact surface between each semiconductor element and the portion being lower than or equal to 0.5 um.

Abstract: An electronic device which includes at least one optoelectronic component including a first active layer, a first electrode, and a second interface layer between the first layer and the first electrode; and at least one first field effect transistor including a first semiconductor portion, a first gate, and at least one third layer, between the first gate and the first semiconductor portion. The third layer is made of the same material as the second layer. The electronic device includes a second electrode and a fourth interface layer between the first layer and the second electrode and includes a second field effect transistor that includes a second semiconductor portion, a second gate, and at least one fifth layer between the second gate and the second semiconductor portion. The fifth layer is made of the same material as the fourth layer.

Abstract: An optoelectronic circuit including a full-wave rectifier circuit including light-emitting diodes and a circuit limiting the current passing through the light-emitting diodes.

Abstract: An image sensor having a portion including interconnection levels formed on a semiconductor substrate covered with a first layer of a dielectric material, including conductive tracks separated from one another by insulating layers interconnected by vias crossing the insulating layers, and an infrared bandpass filter comprising filter levels adjacent to the interconnection levels formed by an alternation of second layers of the dielectric material and of silicon layers, the refraction index of the dielectric material being smaller than 2.5 at the maximum transmission wavelength of the filter, one of the second dielectric layers of each filter level being identical to the insulating layer of the adjacent interconnection level.

Abstract: A photodetector including a photoelectric conversion structure made of a semiconductor material and, on a light-receiving surface of the conversion structure, a stack of first and second diffractive elements, the second element being above the first element, wherein: the first element includes at least one pad made of a material having an optical index n1, laterally surrounded with a region made of a material having an optical index n2 different from n1; the second element includes at least one pad made of a material having an optical index n3, laterally surrounded with a region made of a material having an optical index n4 different from n3; the pads of the first and second elements are substantially vertically aligned; and optical index differences n1?n2 and n3?n4 have opposite signs.

Abstract: A memory array including: a first volatile memory cell including first and second cross-coupled inverters between first and second storage nodes; a first non-volatile memory cell including at least one resistive element that can be programmed to take one of at least two resistive states; and a control circuit adapted to couple the first non-volatile memory cell to the first and second storage nodes in order to generate a current for programming the resistive state of the at least one resistive element.

Abstract: A method for detecting electric arcs in a closed chamber having no openings larger than 5 mm and defining a gas volume to be monitored. The method includes a step of measuring a sound level captured by a microphone, placed inside the chamber, at frequencies greater than about 60 kHz while filtering out the lower frequencies, and a step of comparing the level with a threshold.

Abstract: A clock receiver including: a ring oscillator adapted to generate a clock signal, the ring oscillator having a sequence of N inverters, an input of a first inverter being coupled to a feedback node, an input of a second inverter being connected to an output of the first inverter and to an input line for receiving a reference clock signal, and an output of the second inverter or of a third inverter providing a first phase signal; a further sequence of inverters, an input of a first further inverter being coupled to the feedback node, and an output of another further inverter providing a second phase signal; and a control circuit for adjusting an oscillation frequency of the ring oscillator based on the relative phases of the first and second phase signals.