Abstract: A software program is used in conjunction with a standard general purpose multi-processor computer system as a means of implementing an I2O-compliant input-output processor (“IOP”) without requiring a special hardware IOP processor embedded on a PCI device card and connected to a computer system PCI bus. At least one of the multi-processor is targeted for operating a special software operating system module. The special software operating system module is capable of emulating the I2O-compliant input-output operating system program. This enables the targeted CPU to act as a virtual IOP.

Abstract: Methods and arrangements are provided that allow for data communications between a plurality of devices over a reduced bandwidth communication medium, such as, for example, a twisted pair wire as used in many home environments for telephone access. The methods and arrangements advantageously reduce the necessary bandwidth required for a data communication by eliminating the need to transmit encoded data, such as Manchester encoded data between devices. Thus, for example, Ethernet configured data that is encoded and output by a network interface within a sending device/appliance is intercepted, decoded, transmitted over a reduced bandwidth communication medium, and then re-encoded and re-transmitted or otherwise supplied to the network interface within the receiving device/appliance. For Manchester encoded data signals associated, for example, with a 10 BASE-T Ethernet network, the encoded data signal has a data rate that is twice that of the decoded data signal.

Abstract: A computer system includes a bus bridge which provides an interface between a processor bus, a main memory and a peripheral bus such as a PCI or AGP bus. When a cycle to memory is initiated on the PCI or AGP bus by a peripheral device, a snoop control circuit of the bus bridge arbitrates for the processor bus to initiate a snoop cycle which corresponds to the line being accessed by the peripheral device. In addition to performing a snoop for the current line being accessed, the snoop control circuit further advantageously runs a speculative snoop cycle for the next sequential line. By performing a speculative snoop cycle on the CPU bus to the next line address, latencies associated with subsequent accesses to memory by the peripheral device may be reduced if the device performs a subsequent sequential access. Furthermore, since the bus bridge performs multiple snoop cycles per arbitration cycle (e.g.

Abstract: A handheld computer which contains an LCD display having a digitizing surface to allow pen input. Internal storage takes several forms, such as a large flash ROM area, battery-backed up RAM and an optional hard disk drive. Several alternative communication paths are available, such as the previously mentioned modem, a parallel printer port, a conventional serial port, a cradle assembly connected to the host computer, and various wireless short distance techniques such as radio frequency or infrared transmission. The computer can readily communicate with other sources, particularly to a host desktop computer, to allow automated synchronization of information between the host and the handheld system. Preferably the remote synchronization is performed at several user selectable levels. When the handheld computer is in a cradle and actively connected to the host computer, automatic capture of updated data in the host computer is performed.

Abstract: A SCSI bus expander provides signal conditioning for transmitted data pulses that is particular to a negotiated data transfer rate. The expander monitors the bus arbitration to determine the devices involved in the transfer, and thereafter monitors the data transfer rate negotiations to determine the transfer rate to be used by that particular combination of devices. An indication of the transfer rate is stored in a memory device at an address determined by the device IDs. The transfer rate is then used to select tap values for tap lines that modify the pulse width and/or a propagation delay of the pulse, so as to correct for signal degradation and to align it better relative to other signals during data transmission. The specific tap values may vary for the different combinations of transmitting and receiving devices involved in the transfer, since the manner in which the pulse characteristics should be modified may be different for different transmission rates.

Abstract: A cooling assembly for cooling a CPU on a motherboard in a low profile electronic device. The assembly comprises a channel-shaped heat sink having a flat first wall, an opposite wall, open first and second ends and internal heat exchange fins extending between those walls and ends. An electric blower having an inlet and an outlet is mounted to the heat sink so that the blower outlet is aligned with the first end of the heat sink and the heat sink is anchored to the CPU so that the first wall of the heat sink is flush against the CPU and the blower inlet overhangs an edge of the motherboard. Preferably, a baffle member is mounted to the heat sink to direct heated air from the second end of the heat sink to the atmosphere and to prevent recirculation of that air back to the blower inlet.

Abstract: An electronic apparatus, e.g., a lap top computer, has an enclosure which on its inner surface is coated with a phase-change material, e.g., in micro encapsulated form, preferably mixed with paint which is used to coat the inner surface of the enclosure. The phase change material absorbs heat generated by components in the electronic apparatus and maintains the components in the apparatus at a reasonable temperature.

Abstract: The invention provides computer apparatus for performing a division operation having a dividend mathematically divided by a divisor. The dividend and the divisor are split between a state machine and an array of carry save adders. The most significant bits of the dividend and the divisor are input to the state machine and the least significant bits of the dividend and the divisor are input to the carry save adder array. The state machine is fully encoded with partial remainder values and quotient digit values for all possible combinations of the most significant bits of the divisor and the dividend. The carry save adders add the respective least significant bits of the dividend and the divisor and output spillover signals to the state machine. The state machine provides partial remainders and quotient digits selected from the encoded partial remainder values and quotient digit values dependent on (i.e. as a function of) the most significant bits of the dividend, divisor and the spillover signals.

Abstract: A database query compiler and compilation method has special facilities for compiling a query that includes one or more of a predefined set of running and moving sequence functions. The compiler converts the query into a predefined normalized form suitable for compilation using a running and moving function normalizer. The running and moving function normalizer converts each running and moving sequence function in the set into a corresponding ordered set of one or more executable statements, which include at least one Offset sequence function that accesses data in an auxiliary field of a row of a table. An offset sequence function compiler, compiles each Offset sequence function, Offset(argument, index), in the normalized database query into a compiled set of instructions, including instructions for storing and reading the auxiliary fields to and from a buffer that is separate from the table. The buffer is preferably stored in volatile, main memory.

Abstract: A system for identifying the file structure of a computer program, preserving the file structure of the code after translation of source code from one high-level computer language to another, combining pieces of a source file that were generated in different translation sessions, and ensuring textual consistency of each piece of generated code in the resultant code files.

Abstract: A method for configuring communications settings in a computer system is provided. The method includes receiving a configuration settings file. The configuration settings file includes global connection settings, a connection type, and connection type specific settings. A communications link is configured to address a service provider based on the global settings. An access device in the computer system is configured based on the connection type and the connection type specific settings.

Abstract: A computing apparatus connectable to a cache and a memory, includes a system port configured to receive an atomic probe command or a system data control response command having an address part identifying data stored in the cache which is associated with data stored in the memory and a next coherence state part indicating a next state of the data in the cache. The computing apparatus further includes an execution unit configured to execute the command to change the state of the data stored in the cache according to the next coherence state part of the command.

Abstract: Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used.

Abstract: An interconnectivity scheme for a PC Theatre system includes the use of compatible plug and display connectors on both the display and the host computer. Audio/video signals received by either the display or the computer may be processed by the computer and transmitted between these devices in a standardized signal format using the compatible connectors. The control scheme for facilitating master-slave control of the display by the computer includes the use of various standardized signals and formats as well to ensure compatibility between products manufactured by different companies.

Abstract: The invention recognizes that a probability density function for fitting a model to a complex set of data often has multiple modes, each mode representing a reasonably probable state of the model when compared with the data. Particularly, sequential data such as are collected from detection of moving objects in three dimensional space are placed into data frames. Computation of the probability density function of the model state involves two main stages: (1) state prediction, in which the prior probability distribution is generated from information known prior to the availability of the data, and (2) state update, in which the posterior probability distribution is formed by updating the prior distribution with information obtained from observing the data. In particular this information obtained purely from data observations can also be expressed as a probability density function, known as the likelihood function.

Abstract: A high voltage flyback power supply provides slope-based primary feedback to control the off-time of the power supply. When a negative slope is detected at a low side of a primary winding of the power supply, an off-time cycle is terminated and a next on-time cycle is initiated. The slope-based off-time primary feedback helps to keep the off-time of the power supply in sync with ringing of the primary leakage inductance and the primary-side capacitance of the power supply. Such a power supply is particularly useful for battery-powered systems with low voltage rails. The power supply can also include on-time feedback to shorten the on-time of the power supply after the secondary-side voltage rises beyond a certain relatively high voltage level. In this way, the transformer of the power supply is charged less when the power supply is driving relatively light loads.

Abstract: According to the present invention, an apparatus having a plurality of independently operable and powerable devices is disclosed. The apparatus includes a plurality of power rails, a plurality of ground planes, and a power management circuit. One of the power rails is associated with one of the plurality of independently operable devices. One of the plurality of ground planes is selectively associated with one or more of the plurality of power rails. The power management circuit couples to the plurality of power rails and the second plurality of ground planes, for selectively deactivating at least one of the plurality of ground planes independently of any of the other plurality of power rails.

Abstract: A space-efficient, multi-cycle barrel shifter circuit for shifting data inputted into the circuit by a shift value over multiple clock cycles which circuit includes: (a) a load module adapted to receive a load signal and the data, the load module coupled to the shift module and configured to load the data into the shift module upon receipt of a load signal; (b) a register module coupled to the shift module and to the load module, where the register module is a register adapted to receive a clock signal and configured to pass the data through the shift module with each clock cycle; (c) a constant shift module coupled to the register module and the shift module and configured to shift the data by a constant amount with each clock cycle; and (d) a control module coupled to the shift module and the load module, the control module capable of generating a command signal for each elementary shifter in the shift module for each clock cycle based upon the shift value, the command signal determining the amount of shift

Abstract: A method for configuring storage devices includes detecting an existing storage device configuration. The existence of a new storage device is detected, and the new storage device is configured based on the existing storage device configuration. A computer system includes an existing storage device, a new storage device, and a processor. The existing storage device has an existing storage device configuration, and the processor is adapted to detect the existence of the new storage device and configure the new storage device based on the existing storage device configuration.

Abstract: A system and method for hardware assisted formatted data transfer allows a formatting storage controller to read and record data on a formatted storage medium and avoids a requirement of continuous interaction by a host system in the transfer process. The host system can initiate the transfer process by sending a command block, a data definition, and an on-media structure definition to a formatting storage controller, which performs the formatted transfer and notifies the host system when the transfer is completed or an exception occurs. Alternately, the formatting storage controller can access one or more on-media structure definitions stored in a persistent storage unit in accordance with an on-media structure selector provided by the host system in the command block.