Abstract: A cluster administration system that is capable of handling a cluster having one or more computing devices. The number of computing devices that may be included in a cluster is limited only by practical considerations rather than software or hardware limitations. A cluster administration system may include a cluster of computing devices, one of the computing devices being an owner. The cluster further includes a resource. Direct access to the resource by the computing devices is controlled by the owner of the cluster. The cluster administration system also includes an arbiter. The arbiter and the cluster are in communication with each other and a network, the cluster providing the network with access to the storage device. The arbiter controls the admission of new computing devices to the cluster when the owner of the cluster is incapable of admitting the new computing device. Having the arbiter outside the cluster provides greater reliability. The arbiter is not affected by failures within the cluster.
Abstract: A computer system including a microprocessor and a circuit to provide a clock signal for the microprocessor is described. The circuit is responsive to a control signal for selecting a minimum clock signal frequency value and a maximum clock signal frequency value, with the maximum clock signal frequency value being adjusted in accordance with operating conditions of the central processor. Also the system includes a circuit which varies a magnitude of a supply voltage fed to the microprocessor in accordance with the temperature of the microprocessor and the operating frequency of the microprocessor. This arrangement provides an advantage to save power in computers. It is particularly advantageous for portable computers such as notebook computers to conserve battery charge, minimize heat dissipation in the microprocessor, and to minimize the size and weight of the battery used in the notebook for a given operating duration requirement.
Type:
Grant
Filed:
October 11, 1994
Date of Patent:
October 30, 2001
Assignee:
Compaq Computer Corporation
Inventors:
Richard J. Dischler, Jim Klumpp, Reinhard Schumann
Abstract: A system includes a memory module formed of a first portion having a first side that directly connects to a mount in the system, which first side is of a first length; and a second portion having a second side, which second side is of a second length, the second length being greater than the first length. The second side may comprise an arcuate form or a plane that is different from the plane of the first side. Each of the first and second portions is used for affixing a memory element.
Type:
Grant
Filed:
October 31, 1996
Date of Patent:
October 30, 2001
Assignee:
Compaq Computer Corporation
Inventors:
Robert W. Noonan, Jeffrey L. Hooten, Christian H. Post
Abstract: A method and apparatus for providing uninterrupted DC power for network nodes. The uninterrupted DC power is derived from modular, stackable uninterruptible power supplies that fit within the housing of the network node. Because the battery of the uninterruptible power supply is charged from a DC output of a main power supply, only one AC/DC power converter is required. A high degree of efficiency is therefore obtained.
Abstract: A scheme may be used to replace a processor in a multiprocessor computer without the need for turning the computer off to replace the processor. In this scheme, all of the processors on the bus are placed into sleep mode. Then, power is disconnected from the processor to be replaced, and the processor is removed. The replacement processor is then powered up and configured in the same manner as the processor it replaced. The replacement processor is then placed into return the computer to normal operation without the need to reboot the computer.
Abstract: A computer system which includes an electromagnetic hoodlock, and does not have any simple way to bypass the hood-lock The hoodlock consists of a spring-loaded solenoid, and is controlled by the system microprocessor. The system chassis may only be opened by a user with sufficient rights, after entering a password, or after an administrative command is sent over the computer network.
Type:
Grant
Filed:
August 31, 1998
Date of Patent:
October 23, 2001
Assignee:
Compaq Computer Corporation
Inventors:
Robin T. Tran, Christopher Simonich, Michael R. Durham, Lee B. Hinkle
Abstract: In a computer processor module/heat sink assembly, a spring clip member is used to resiliently hold a heat-generating die portion of the processor against the heat sink. Spaced retaining pins are secured to the processor module and extend through holes in the heat sink, with outer end portions of the retaining pins being captively retained in slots in the spring clip member, and portions of the clip member adjacent the outer pin ends being resiliently deformed toward the outer side of the heat sink to thereby resiliently press the processor die portion against the underside of the heat sink. The clip member may be quickly installed on and removed from the outer pin ends without the use of tools of any sort.
Type:
Grant
Filed:
July 8, 1999
Date of Patent:
October 23, 2001
Assignee:
Compaq Computer Corporation
Inventors:
Arthur K. Farnsworth, Francis A. Felcman, Donald J. Hall
Abstract: A wireless communication device includes a housing, a user input device mounted in the housing, and a number of LEDs located so as to produce light from the housing, wherein at least two of the LEDs are located an appreciable distance apart from each other on the housing.
Abstract: A semi-mobile desktop personal computer incorporating the features of a desktop personal computer with the mobility of a mobile personal computer. The computer includes a system enclosure attached to a storage enclosure, the storage enclosure extends outside the system enclosure and provides stability for the system enclosure by engaging the surface on which the system enclosure has been placed for use.
Abstract: A method and apparatus of allocating memory space in a main memory of a computer system to a unified memory architecture device. The main memory is associated with a physical address space. A required linear address range is determined for the video card, and the linear address range is mapped to scattered portions in the physical address space. A page table is created containing page frame numbers corresponding to page frames in the main memory, the page frames being allocated to the device. The page frames are non-contiguous blocks of the main memory. The device is associated with a linear address space. The frame numbers are loaded into a translation look-aside buffer (TLB) for converting a linear address in the linear address space to a physical address in the physical address space.
Type:
Grant
Filed:
December 31, 1996
Date of Patent:
October 23, 2001
Assignee:
Compaq Computer Corporation
Inventors:
Mark W. Welker, Michael P. Moriarty, Thomas J. Bonola
Abstract: A portable computer has a base housing to which a display housing is pivotally secured for movement between open and closed orientations. Extending across a top side opening of the base housing is a keyboard assembly which may be removed from the top side of the base housing. The removed keyboard assembly may be vertically supported on a rear portion of the base housing, to permit access to the base housing through its now exposed top side opening, by means of tabs formed on a rear side edge of the keyboard support plate structure and removably insertable in corresponding vertically extending slots in the top side wall of the base housing. This vertical support of the removed keyboard assembly prevents it from being misplaced, reduces the potential for damaging it by laying it aside on an adjacent work space area, holds the vertically supported keyboard assembly away from the display screen to prevent the keyboard assembly from scratching it.
Abstract: A computer system using a queuing system and method for managing a queue having a plurality of generic queue headers connected together by a plurality of links in a predetermined manner. Each generic queue header may be attached to one of a plurality of data structures. The queuing system also includes a library of queue function calls for controlling the operations of each one of the plurality of generic queue headers.
Abstract: A method for decompressing compressed data elements, drawing that decompression operation, the intermediate coefficients are organized in a matrix configuration such that the number of transpose operations are minimized. The organization of that matrix includes storing sequential coefficients, translated from the compressed data, in sequential locations of sequential columns of the matrix. The transpose operation is performed during the inverse discrete cosine operation portion of the decompression operation.
Type:
Grant
Filed:
December 24, 1998
Date of Patent:
October 16, 2001
Assignee:
Compaq Computer Corporation
Inventors:
Matthew Adiletta, Robert Stepanian, Teresa Meng
Abstract: A manually operable ejector assembly is mounted on the front side of a carrier that supports a hot-pluggable disk drive for removable slidable insertion into a sheet metal cage structure portion of a computer system. The ejector assembly includes a main ejector lever which is pivotally spring-biased in a forward direction outwardly from the front side of the carrier, and is releasably held in a pivotally retracted position by a slide bar member that is spring-biased toward a retaining position in which it overlies a free end of the ejector lever. To remove the carrier from the cage, the slide bar member is slid away from the free ejector lever end, thereby permitting the lever to be spring-driven outwardly to an intermediate open position in which it conveniently forms a pull-handle but does not disconnect the drive from the backplane connector.
Abstract: A database management system is extended to process SQL statements so as to skip over rows that are locked in conflicting modes. Normally, a table access operator is blocked when it attempts to access a row that is locked in a conflicting mode, such as a write lock mode, that is inconsistent with the read or write access required by the operator. Generally, the lock in the conflicting mode will be held by a transaction other than the transaction associated with the operator in question. When the SQL statement being executed uses the “skip conflict” syntax provided by the present invention, the operator skips over rows that are locked in conflicting modes, which would otherwise cause the operator to suspend operation. Furthermore, if the operator is operating in streaming mode, a key that identifies such skipped rows is added to the operator's list of rows to be processed at a later time.
Type:
Grant
Filed:
July 6, 1999
Date of Patent:
October 16, 2001
Assignee:
Compaq Computer Corporation
Inventors:
Johannes Klein, Robbert C. Van der Linden, Raj K. Rathee
Abstract: A method for improving spatial impression in a four-speaker system using dynamic and piezo transducers. The use of a piezo transducer eliminates the need for a low-pass filter.
Abstract: An accelerated video controller operates in conjunction with a video driver to accelerate certain video operations. If the operating environment requests a polygon operation, the driver (or software on the video controller) will determine whether the specified polygon is simple convex. The determination of whether a convex polygon is simple convex is accomplished by tracing between the vertices of the polygon and comparing the changes in direction relative to a predetermine coordinate axis to a threshold number. If the polygon is simple convex, certain operations can be performed using simpler code or hardware accelerated features. For a polygon fill, if the polygon is simple convex, the edges of the polygon are inspected to determine whether the polygon can be decomposed into a rectangle and a smaller polygon. If so, the video controllers bit engine will be used to perform the fill of the rectangle at high speed, thus reducing the time of the operation.
Abstract: A computer system includes a plurality of processor buses, and a memory bank. The plurality of processors is coupled to the processor buses. At least a portion of the processors have associated cache memories arranged in cache lines. The memory bank is coupled to the processor buses. The memory bank includes a main memory and a distributed coherency filter. The main memory is adapted to store data corresponding to at least a portion of the cache lines. The distributed coherency filter is adapted to store coherency information related to the cache lines associated with each of the processor buses. A method for maintaining cache coherency among processors coupled to a plurality of processor buses is provided. Lines of data are stored in a main memory. A memory request is received for a particular line of data in the main memory from one of the processor buses. Coherency information is stored related to the lines of data associated with each of the processor buses.
Abstract: A computer system is provided which includes features enhancing its serviceability. In a described embodiment, a computer has a chassis which includes option card module latching structures and a drive bay module pivot structure. The latching structures provide convenient access to a system board of the computer. The pivot structure provides convenient access to storage media devices in a drive bay module of the computer.
Type:
Grant
Filed:
April 14, 1998
Date of Patent:
October 9, 2001
Assignee:
Compaq Computer Corporation
Inventors:
Francis A. Felcman, Jerome S. Conway, Hasan Giray Kaya
Abstract: A security methodology and security logic for protecting Plug and Play computer system components from unauthorized access. The security logic prevents modification of the base addresses of specified Plug and Play computer system components by blocking writes to specific index locations programmed into security registers. In the disclosed embodiment of the invention, the base address of a Super I/O chip is protected, as well as the base addresses of specified logical devices in the Super I/O chip. Protecting the base addresses in this manner prevents the security logic from being circumvented by interfering with the address decoding used to track reads and writes to protected index registers. In addition, the security registers are programmed to prevent access to the protected index registers of the logical devices.