Abstract: A docking station for a portable computer has a top side from which peripheral rib structures upwardly project and form a receiving and holding area into which the computer may be lowered in preparation for docking. The receiving and holding area complementarily receives the computer, with the rib structures preventing the computer from shifting parallel to the top docking station side. A lever structure is then manually pivoted to responsively move a docking station electrical connector relative to the stationary computer into a releasably mated relationship with a corresponding connector on the computer to complete the docking process. The rotation of the docking lever also interlocks a security latch member with the computer to block its upward removal from the docking station. A Kensington lock may be used to hold the lever in its docking orientation, and thus keep the security latch interlocked with the docked computer.

Abstract: A computer's representation and handling of dial-up and network applications are standardized. A LAN connection is established on a session basis only when required, enabling a user or system administrator to have the same control over the LAN connection as is typically exercised over a WAN connection. Examples of WAN connection features that are available to the LAN connection are the maintenance of billing information, access control, authentication and verification. In addition, an application can be represented by several different icons configured to utilize different procedures and communication devices.

Abstract: A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: A method and apparatus are disclosed for attenuating RF noise produced by electronic systems by providing low RF impedance shorting of heat dissipating structures, such as heat sinks, to PCB reference planes. The RF impedance shorting path uses existing package pins with dedicated electrical paths through the package to the bottom surface of the heat sink. Such an arrangement provides very low RF impedance because of the minimal length and resistance of the shorting path, and also provides minimal disruption of the PCB design rules and tolerances by using existing package leads.

Abstract: A computer system is capable of playing audio CDs in a CD-ROM drive independent of the operating system by using an embedded CD-ROM drive application or a CD-ROM drive controller. When an audio CD mode switch of the computer system is in an “on” state and the main power switch of the computer is in an “off state” the computer system is in an audio CD mode. When the computer is placed in such an audio CD mode, the computer either loads the embedded CD application from a non-volatile memory region such as read-only-memory (ROM) region or enables the CD-ROM drive controller of the CD-ROM drive to receive a CD selection and transmit the selections to the CD-ROM drive.

Abstract: A method and apparatus that operates within a virtual memory system in which portions of the memory system can be “omnibus wired,” Omnibus wiring a page guarantees that the page is present in memory and that the mapping tables pointing to the page's location are also present and filled in for all possible address references to the page. Because the system is which the present invention is implemented allows memory sharing between processes, there can be several virtual addresses that address a single page. Various elements in the virtual memory system include a “cached MSCR” field. The cached MSCR field is used to determine whether it is necessary to continue recursing upwards when performing omnibus wiring, since there is a special case associated with “uplevel references” and omnibus wiring.

Abstract: A method and apparatus that operates within an object oriented virtual memory management system. The invention relates to invalidating mapping tables that are pointed to by PMOs (Partitioned Memory Objects). The PMOs specify locations of pages within the entire memory space of a process. The mapping tables specify locations of pages that have been swapped into a primary memory. In a preferred embodiment of the present invention, each PMO includes a plurality of MORs. Each MOR includes an involved bit. When a page is swapped into memory, the involved bits in all MORs relating to the page are set (except for the last MOR on a level). When a page is swapped out of memory, the present invention allows the mapping tables for the page to be invalidated in an efficient manner. Once a MOR having an involved bit clear is detected, there is no requirement to invalidate additional mapping tables for the path.

Abstract: An apparatus and method for synchronizing a cache mode in a cache memory system in a computer to protect cache operations. The cache memory system has a first controller and a second controller and two cache modules and operates in a plurality of cache modes. The cache mode is stored as metadata in the cache modules and is detected by the first controller to determine the cache mode. Lock signals in the first controller are set in accordance with the cache mode detected to set the cache mode state in the first controller. The second controller copies the cache mode state from the first controller to synchronize both controllers in the same cache mode state. After a failure of the second controller, the first controller may lock access to both caches to recover data previously accessed by the second controller. The second controller restarts and copies the cache mode state from the first controller, so that both controllers return to the cache mode state prior to the failure of the second controller.

Abstract: The invention pertains to serializing local and remote references to a portion of a shared memory to optimize sequencing of requests in a switch-based, multi-processor system in which the local and remote references can occur concurrently. Usually, local accesses are typically much faster than remote accesses. Thus, in the interest of performance, both local and remote accesses are permitted to occur concurrently in the multiprocessing system. However, in one instance a local access can cause deadlock problems for a remote access. In addition, problems associated with coherency of the shared memory can also arise. Thus, in order to prevent deadlock problems and to maintain coherency of a shared memory, if a local reference to an address of memory has been forwarded to a switch, in this instance a hierarchical switch, then all subsequent references to that address of memory are forwarded to the hierarchical switch. The hierarchical switch has ordering properties that maintain the received order of inputs.

Abstract: A computer system includes a CPU and a memory device coupled by a bridge logic unit. CPU to memory write requests (including the data to be written) are temporarily stored in a queue in the bridge logic unit. The bridge logic unit preferably begins a write cycle to the memory device before all of the write data has been stored in the queue and available to the memory device. By beginning the memory cycle as early as possible, the total amount of time required to store all of the write data in the queue and then de-queue the data from the queue is reduced. Consequently, many CPU to memory write transactions are performed more efficiently and generally with less latency than previously possible.

Abstract: A bridge logic unit provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to memory bus, and a peripheral device coupled to a peripheral bus, such as a PCI bus. To maintain coherency, the bridge logic unit disables write posting in certain specific situations, and flushes posted write transactions before allowing certain read requests to be serviced. More specifically, in one embodiment when a PCI device performs a read to main memory, which may be implemented within the bridge as delayed read, the bus bridge blocks CPU to PCI transactions and flushes any posted CPU to PCI transactions pending in the bridge. The bus bridge enables CPU to PCI posting after the pending CPU to PCI transactions have been flushed and after the snoop phase of a snoop cycle corresponding to the memory read operation completes.

Abstract: An apparatus for dithering a signal such as a pixels of an image having multiple address dimensions. A predetermined number of least significant bits of a first address of the pixel are used to index a one-dimensional dither array. Indexing the array produces a first dither value. A predetermined least number of significant bits of a second address of the pixel are combined with the first dither value to index a second one-dimensional dither array. The indexing of the second array produces a final dither value that can be used to dither the pixels.

Abstract: In a computer system having at least one host processor, a method and apparatus for providing seamless hooking and interception of selected entrypoints includes finding the IDT for each CPU which can include scanning the HAL image for the HAL PCR list. Saving the interrupt handler currently mapped in the CPU's interrupt descriptor table. Patching the original interrupt into the new interrupt handler. Storing the new interrupt exception into the CPU's interrupt descriptor table. Hooking a select entrypoint by first determining if the entrypoint begins with a one byte instruction code. If it does, saving the address of the original entrypoint, saving the original first one byte instruction, and patching the new interrupt intercept routine to jump to the original entrypoint's next instruction.

Abstract: A system and method for displaying tracked objects on a display is disclosed The method includes writing current location and a number of previous locations of the object with pixel values having non-zero overlay data. The system writes an ordered set of codes into the pixel values for the current location and indicates the set to a driver. The driver uses the overlay data displaying the current and several previous object locations sequentially in order of the set. The displayed locations may be displayed by unmasking the overlay data. The codes may be index values in the pixel values indicating corresponding entries in a pixel interpretation table. A driver may modify mask values in the table entries to mask or unmask overlay data in associated pixel values. The system can display many tracked objects simultaneously, without high CPU utilization or a program to draw, erase, and redraw tracked objects.

Abstract: A computer system including a serial bus host controller and host controller driver. The host controller driver providing data structures for the host controller to operate on. The data structures having a linking mechanism for processing lists of descriptors, and alternate buffer configurations for receiving data from the serial bus devices.

Abstract: A network controller system including multiple network ports and a driver system that programs each of the network ports with a common multicast address and that operates the network ports as a team. The team is operated to form a virtual device in one of several team modes, such as fault tolerance or load balancing, to enhance performance of communication of the computer in a network. The driver system commands at least one of the network ports to transmit a multicast heartbeat packet, where each of the other network ports receives and transfers the multicast heartbeat packet to the driver system. In this manner, the driver system need only send one multicast heartbeat packet to test all of the other network ports. Two network ports are selected to each send a heartbeat packet to test each other heartbeat port and the remaining ports.

Abstract: The outcome of a plurality of branch instructions in a computer program is predicted by fetching a plurality or group of instructions in a given slot, along with a corresponding prediction. A group global history (gghist) is maintained to indicate of recent program control flow. In addition, a predictor table comprising a plurality of predictions, preferably saturating counters. A particular counter is updated when a branch is encountered. The particular counter is associated with a branch instruction by hashing the fetched instruction group's program counter (PC) with the gghist. To predict multiple branch instruction outcomes, the gghist is hashed with the PC to form an index which is used to access naturally aligned but randomly ordered predictions in the predictor table, which are then reordered based on value of the lower gghits bits. Preferably, instructions are fetched in blocks of eight instructions.

Abstract: A computer system is provided with a non-volatile memory module that is shared by a plurality of system components during system initialization. In one embodiment, the computer system comprises a processor for executing program instructions, a memory device for storing data and program instructions, a number of integrated system components for carrying out specialized functions, a bridge logic device for communication between the processor, memory, and system components, and a shared non-volatile memory module for storing configuration information for each of the system components. Each of the integrated system components is configured to retrieve its associated configuration information from the shared non-volatile memory module during initialization, rather than from a dedicated non-volatile memory as is conventionally done. This consolidation of multiple non-volatile memories into a single memory module provides numerous advantages including reduction of cost and required space on the motherboard.

Abstract: Electrical signals are received corresponding to sets of digital data, and output optical signals are delivered, corresponding to the digital data, on at least two optical channels corresponding to different sets of the digital data, using light from a single light source. In another scheme, the optical switch may be integrated with an optical transmission medium (e.g., an optical cable).