Abstract: A technique for controlling a presentation of a computer generated object having a plurality of movable components is disclosed. In one embodiment, the technique is realized by receiving a gesture element and an audio element at a processing device. The gesture element represents a gesture involving one or more of the plurality of movable components. The audio element represents an audio signal. The processing device receives the gesture element and the audio element in a sequential order. The processing device processes the gesture element and the audio element in the sequential order so that each of the plurality of movable components associated with the gesture element are moved to perform the gesture and the audio signal associated with the audio element is generated during a presentation of the computer generated object. The gesture can be performed and the audio signal can be generated simultaneously.

Abstract: A computer system that includes a CPU, a memory and a memory controller for controlling access to the memory. The memory controller generally includes arbitration logic for deciding which memory request among one or more pending requests should win arbitration. When a request wins arbitration, the arbitration logic asserts a “won” signal corresponding to that memory request. The memory controller also includes synchronizing logic to synchronize memory requests, corresponding to a first group of requests, that win arbitration to a clock signal and an arbitration enable signal. The synchronizing logic includes an AND gate and a latch for synchronizing the won signals. The memory controller also asynchronously arbitrates a second group of memory requests by asserting a won signal associated with the second group requests that is not synchronized to the clock signal.

Abstract: A method and apparatus for identifying devices on a network. A management device is configured to multicast a query message to request identification of network devices. Each of the network devices is configured to respond to the management device multicast message by transmitting a reply message containing identification information of the responding device. The management device includes a directory containing the identification information of the network devices. The network protocol can include the TCP/IP protocol, and the packets have a format complying with a bootstrap protocol.

Abstract: A bus configuration and associated termination for an Intel Slot 2 bus supporting communication for at least one Intel Pentium II Xeon processor. The Intel Slot 2 bus is configured in an in-line topology and includes a plurality of Intel Slot 2 bus connectors connected to the Intel Slot 2. A first plurality of bus terminators are electrically connected to a first end of the in-line Intel Slot 2 bus and a second plurality of bus terminators are electrically connected to a second end of the in-line Intel Slot 2 bus. The first and second plurality of bus terminators are constructed in accordance with termination specifications required by Intel on terminator cards which are inserted into unpopulated Intel Slot 2 bus connectors except that one end of the bus has the one hundred and fifty ohm pull-up resistor required by Intel replaced with an eighty two ohm pull-up resistor.

Abstract: Application programs can dynamically link to multiple transports by attaching and detaching vectors (jump addresses, i.e., entry points to the functions provided by third party transport stack/drivers) of third party transport stack/drivers in a dynamic manner. Notify callbacks are made from the transport stack/driver, allowing asynchronous operation without requiring the application to wait for the transport stack/driver to confirm a network transport operation.

Abstract: A manually operable ejector assembly is mounted on the front side of a carrier that supports a hot-pluggable disk drive for removable slidable insertion into a sheet metal cage structure portion of a computer system. The ejector assembly includes a main ejector lever which is pivotally spring-biased in a forward direction outwardly from the front side of the carrier, and is releasably held in a pivotally retracted position by a slide bar member that is spring-biased toward a retaining position in which it overlies a free end of the ejector lever. To remove the carrier from the cage, the slide bar member is slid away from the free ejector lever end, thereby permitting the lever to be spring-driven outwardly to an intermediate open position in which it conveniently forms a pull-handle but does not disconnect the drive from the backplane connector.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: A method and apparatus for comparing the real time operation of two object code compatible processors to discover incompatibilities and provide fault-tolerance in a computer system. The two processors run the same code and compare their write operations in real time. Logic external to the processors arbitrates between them, granting only one processor access to the system bus at any one time. The first processor executes instructions until it reaches a write or I/O data read cycle, at which time control of the system bus passes to the second processor. The second processor executes the instructions previously executed by the first processor until it catches up to the cycle pending on the first processor. If this cycle is a write cycle, then error detection logic compares the signals pending on the two processors to flag inconsistencies.

Abstract: A method and apparatus for performing failover recovery in a network server. A first network server, operating within a communication network, is initialized to operate in a failover recovery mode. The network server includes a host computing system for controlling operation of the server and an Input/Output subsystem for controlling operation of peripheral devices associated with the first server. A communication link effectuates communication between the first server and a second network server. A heartbeat generator, located within the first server, generates a periodic heartbeat signal when the host computing system of the first server is functioning normally. A heartbeat timer, located within the Input/Output subsystem of the first server, detects an absence of the heartbeat signal by counting elapsed time between successive heartbeat signals.

Abstract: A server extension architecture provides means for intercepting input events and output protocol requests. Remote terminal emulation on an XWindows system is possible. The architecture comprises a portion of memory in the server extension which is identical to a portion in memory in the server where the server stores the addresses of input and output handling routines. By swapping these addresses with addresses in the server extension portion of memory, the server extension intercepts input and output, for monitoring a server or an application program or controlling a workstation. The server extension architecture is operated under the control of an application program.

Abstract: A modular computer includes a portable computer module providing a first set of performance characteristics, an expansion module reversibly couplable to an exterior surface of the portable computer module to provide, in combination therewith, a second set of performance characteristics, and a docking module reversibly couplable both to the portable computer module singly and to the portable computer module when combined with the expansion module to provide, in combination therewith, a third set of performance characteristics. A method of altering the features of a portable computer includes providing a portable computer having a first set of features, operatively coupling the portable computer to a transportable base wherein the coupling provides a second set of features, and operatively connecting the portable computer singly or in combination with the transportable base to a stationary base, wherein the connecting provides a third set of features.

Abstract: A computer system includes a CPU, a memory device, two expansion buses, and a bridge logic unit coupling together the CPU, the memory device and the expansion buses. The CPU couples to the bridge logic unit via a CPU bus and the memory device couples to the bridge logic unit via a memory bus. The bridge logic unit generally routes bus cycle requests from one of the four buses to another of the buses while concurrently routing bus cycle requests to another pair of buses. The bridge logic unit preferably includes four interfaces, one each to the CPU, memory device and the two expansion buses. Each pair of interfaces are coupled by at least one queue; write requests are stored (or “posted”) in write queues and read data are stored in read queues.

Abstract: An integrated circuit is formed having electrical conductors with electromigration-inhibiting/electrically conductive plugs disposed between electrically conductive segments of the electrical conductor. Windows are formed within a planar surface. An electromigration-inhibiting/electrically conductive material is deposited over the planar surface and through the windows to fill the windows and thereby provide, in such windows, plugs of electromigration-inhibiting/electrically conductive material. Portions of the electromigration-inhibiting/electrically conductive material are removed to form the plugs with surfaces co-planar a surface surrounding the plugs. The electrical conductive segments are formed within the same planar surface as the plugs, either before, or after, the plug formation. The electrical conductive segments have surfaces co-planar with the plugs, are aligned with and electrically interconnected through the plugs.

Abstract: A system of computer manufacturing with pre-installation of software which utilizes a software selection process controlled by a rules database to determine the proper software components to be pre-installed onto an assembled computer or hard drive. Additionally, the rules base determines the appropriate diagnostic and set-up software components to be installed in order to ensure a system that is ready-to-run upon receipt by a purchaser.

Abstract: The present invention relates to a system and method for shadowing data of a first register and a second register of a computer system that share a common address. When a bus agent runs a write operation to the register address, retry logic of a first bridge circuit retries the write operation and masks access by the bus agent to the bus. Retry bus master logic reruns the write operation, in response to which the second bridge circuit subtractively decodes the rerun write operation and transfers the data to the second register. The bus agent is then allowed to retry the initial write operation, in response to which the first bridge circuit positively decodes the retried write operation and transfers the data to the first register. Thus, coherency is preserved between the first and second registers.

Abstract: A computer system protects against loss of a computer's volatile data using system ROM and operating system resources. Upon entry into a reduced power state, or sleep mode, the operating system directs device drivers to save the state of hardware registers to RAM. Then, the system ROM saves the contents of RAM to a file in a non-volatile storage medium, such as a hard disk drive. A bit is set in CMOS to indicate completion of this transfer. Upon return from sleep mode, the system ROM clears the CMOS bit and returns to normal operation. However, if a system reboot occurs and the CMOS bit is set, the non-volatile storage file is retrieved, and its contents are restored to RAM. The operating system then directs device drivers to retrieve information from the restored RAM to reinitialize the hardware registers under their control. Thus, the integrity of volatile RAM is maintained following a power loss during a reduced power state.

Abstract: In a computerized method, a moving articulated figure is tracked in a sequence of 2-D images measured by a monocular camera. The images are individually registered with each other using a 2-D scaled prismatic model of the figure. The 2-D model includes a plurality of links connected by revolute joints to form is a branched, linear-chain of connected links. The registering produces a state trajectory for the figure in the sequence of images. During a reconstructing step, a 3-D model is fitted to the state trajectory to estimate kinematic parameters, and the estimated kinematic parameters are refined using an expectation maximization technique.

Abstract: A network device with unified management including at least one port operable at any one of a plurality of media standards, port apparatus coupled to the port(s) that monitors and controls the port(s) for each of the media standards, and a management system that interfaces the port apparatus to manage the port(s) in a unified manner with respect to all of the media standards. The management system manages each of the ports in a unified manner regardless of the particular supported media standards. In one embodiment, the network device includes a memory and maintains multiple sets of statistical information per port. The port apparatus stores the first and second sets of statistics in the memory. The management system receives a statistics request and provides a unified statistic or a corresponding statistic from either the first or the second set of statistics. For port intrusion detection and prevention, one or more ports are assigned one or more authorized source addresses.

Abstract: A technique for sharing a resource among a cluster of devices in a computer network. The technique involves generating a vote count that includes votes from voting devices attempting to form a cluster until the vote count reaches a quorum. The technique further involves, when the quorum is reached, selecting a most advanced generation indicator from among the voting devices, advancing the selected generation indicator and storing the advanced selected generation indicator in memory as a cluster generation indicator. Upon the advanced selected generation indicator being stored in memory, the cluster is formed and includes the voting devices. The technique further involves sharing a resource among the voting devices after the cluster is formed.

Abstract: A computer having a bus interface unit coupled between a CPU bus and a PCI bus and/or a bus interface unit coupled between a PCI bus and memory and or I/O space. The clocking to the configuration space of the bus interface unit can be inhibited to conserve power in two ways. The first approach relies on an input/output address space containing a configuration address register. An enable bit or flag within the configuration address register can be set to allow a determination of the various PCI devices and to configure those devices linked to the PCI bus. Subsequent to computer boot up or initialization, the enable bit can be disabled to disallow further accesses to the configuration address space of the PCI device or PCI compliant bus interface unit. Disabling the enable bit further inhibits or disconnects a clocking signal from sequential logic within the configuration address space to minimize power consumption of the north bridge during its normal operation.