Abstract: A method for transferring data through a bus bridge. The bus bridge includes a number of data buffers for storing data, prefetching data and write posting data. A device communicating with the bus bridge may reserve a buffer by one of two reservation mechanism. The reservation mechanism provides the bus bridge with the address and byte count. The reservation may also be forwarded to any upstream bus bridges. The reserved buffers are prefetched for efficient use of bus access. Data is prefetched and flushed according to alternative algorithms if a buffer is not reserved.

Abstract: An active public user interface in a computerized kiosk senses humans visually using movement and color to detect changes in the environment indicating the presence of people. Interaction spaces are defined and the system records an initial model of its environment which is updated over time to reflect the addition or subtraction of inanimate objects and to compensate for lighting changes. The system develops models of the moving objects and is thereby able to track people as they move about the interaction spaces. A stereo camera system further enhances the system's ability to sense location and movement. The kiosk presents audio and visual feedback in response to what it “sees.

Abstract: In a personal computer system utilizing both a main power supply and an auxiliary power supply, the input and output signal lines of auxiliary powered components are selectively isolated from components powered solely by the main power supply. Gating circuitry and buffer circuitry, controlled by various enable signals, are used to isolate the signal lines. External pull-down or pull-up resistors are no longer required, which frees up printed circuit board area for other components and conserves board space in the computer system.

Abstract: A commander module, coupled to a system bus including system bus control request signals and associated with one of the system bus control request signals, including means for determining whether control of the system bus is required and means for requesting control of the system bus, prior to determining whether such control is required, by asserting the associated system bus control request signal. A computer system including the system bus and at least two such commander modules coupled to the system bus and means for arbitrating for control of the system bus where the arbitrating means are coupled to and responsive to the system bus control request signals.

Abstract: In a computerized image processing system, a camera acquires a set of images of a scene while rotating the camera about an axis passing through an optical center of the camera. The images of the set overlap each other. An initial estimate of the focal length of the camera is made. The initial focal length can be any reasonable focal length. Using the initial estimate of the focal length, the set of images are composited in a memory to determine an estimated initial composited length. A next best estimate of the focal length is derived from the initial estimated composited length. The set of images are recomposed using the next best focal length estimate. This process is iterated until the absolute difference between the successive estimates of the focal length is less than a predetermined threshold to calibrate the camera.

Abstract: A notebook computer has a base housing with a heat-generating microprocessor therein, and a lid housing pivotally connected to the base housing. Operating heat from the microprocessor is transferred to the lid housing, for dissipation therefrom, via a specially designed thermosyphoning heat pipe structure formed from first and second heat pipes. The first heat pipe representatively has a rectangular cross-section, an evaporating portion thermally communicated with the microprocessor, and a coiled condensing portion centered about the lid hinge line and having a circularly cross-sectioned interior side surface portion defined by flat sides of the first heat pipe. The second heat pipe has a circular cross-section, an evaporating portion pivotally received within the coiled first heat pipe portion, and a condensing portion thermally communicated with the lid housing.

Abstract: A computerized method compresses an input sequence of 2-D images captured by a monocular camera. The input sequence of images includes a moving articulated 3-D figure. A pose of the figure in each image is registered using a 2-D scaled prismatic model to produce a state trajectory for the figure in each image of the input sequence. The state trajectory of the figure in the images is reconstructed to determine kinematic parameters of a 3-D kinematic model that best fit the state trajectories, The 3-D kinematic model represents the 3-D movement of the figure in the input sequence of 2-D images. Static information of a first image of the input sequence is encoded. For subsequent images of the input sequence, a time series of state vectors containing the kinematic parameters of the moving figure are encoded. The static information of the first image and the time series of state vectors can be used to generate an output sequence of images including the moving articulated 3-D figure on a viewing device.

Abstract: A method implemented according to the invention relates to a method including the conversion between of logical requirements and physical requirements, including such devices as computer drive arrays, controller/storage box combinations, and conversion of virtual disk drive heights to physical disk drive heights. The methods of the invention can be applied to the configuration of most hierarchical system.

Abstract: A low inductance capacitor mounting structure for capacitors of multilayer printed circuit boards is provided. The capacitor mounting structure includes pads onto which a capacitor is mounted and vias or slots for connecting the solder pads to an upper conductor plane and a lower conductor plane. In the mounting structure, current is carried across the width of the solder pads so that a current in the solder pads flows directly underneath the current in the capacitor. This confinement of the magnetic filed which is between the capacitor and solder pads reduces the inductance of the associated magnetic path. The mounting structure also provides the lower conductor plane slightly below the upper conductor plane. The close spacing of the conductor planes confines a magnetic field, which is around the set of via or slot segments between the two conductor planes, so as to reduce inductance of the associated magnetic path.

Abstract: A data caching system and method includes a data store for caching data from a main memory, a primary tag array for holding tags associated with data cached in the data store, and a duplicate tag array which holds copies of the tags held in the primary tag array. The duplicate tag array is accessible by functions, such as external memory cache probes, such that the primary tag remains available to the processor core. An address translator maps virtual page addresses to physical page address. In order to allow a data caching system which is larger than a page size, a portion of the virtual page address is used to index the tag arrays and data store. However, because of the virtual to physical mapping, the data may reside in any of a number of physical locations. During an internally-generated memory access, the virtual address is used to look up the cache. If there is a miss, other combinations of values are substituted for the virtual bits of the tag array index.

Abstract: A computer system is provided with a multifunction power switch. In addition to the normal function of turning the computer on and off, the power switch has the additional function of clearing CMOS memory. In one embodiment, pressing the power switch while the computer is connected to a power source turns the computer on and off, and when the computer is disconnected from the power source, the CMOS memory may be cleared by pressing and holding the power switch for a predetermined time delay, e.g. 10 seconds. As a precaution against malicious clearing of CMOS memory, activation of this feature may be disabled as long as the computer cover is closed. In this case, the computer cover would have to be at least partially removed before the power button is pressed and held to clear CMOS. An LED may be provided which illuminates to indicate the success of the CMOS clearing operation.

Abstract: In a data storage system a number of records are prefetched from large volume storage devices for transfer to a cache in order to return requested records to a host computer in response to a read request from the host computer. If a previous prefetch is not complete when the read request is received, the number of records in a next prefetch of records is increased by a preset amount. If a previous prefetch is complete, a next prefetch of records is initiated with the same number of records in the prefetch as the previous prefetch. The initiation of prefetch operations is triggered by detection of a sequential read stream in a plurality of read requests from the host computer. When the prefetch size is increased, the preset amount of the increase equals the number of records in the read request from the host computer. After requested records are returned from the cache to the host computer in response to the read request, storage space in the cache used by the returned requested records is released.

Abstract: A data caching system comprises a hashing function, a data store, a tag array, a page translator, a comparator and a duplicate tag array. The hashing function combines an index portion of a virtual address with a virtual page portion of the virtual address to form a cache index. The data store comprises a plurality of data blocks for holding data. The tag array comprises a plurality of tag entries corresponding to the data blocks, and both the data store and tag array are addressed with the cache index. The tag array provides a plurality of physical address tags corresponding to physical addresses of data resident within corresponding data blocks in the data store addressed by the cache index. The page translator translates a tag portion of the virtual address to a corresponding physical address tag.

Abstract: A portable computer system incorporating a multi-purpose status display module that is visible when the main video display is in either an open or locked condition. The status display module is used as an autonomous, real-time battery gauge. The battery gauge display allows a user to monitor the charge status of a battery pack when the system is powered up, when the battery is being recharged by an AC adapter, or when the portable computer is placed into a secondary operating mode. Control signals for the status display are generated by a multi-purpose microcontroller. Battery charge conditions are displayed from 0% to 100% in 10% increments, allowing the computer user to accurately estimate the amount of computing time sustainable by an installed battery pack. The battery gauge display functions independently of the portable computer's operating system, and the computer user need not initiate a software process in order to ascertain remaining battery life.

Abstract: A method and apparatus annotates a computer program to facilitate subsequent processing of the program. Code representing the program is generated at a first computer system. Annotations are generated for the code that provide information about the code. At a second computer, the code is processed according to the information provided by the annotations. The annotations, for example, can indicate a control flow graph representing a flow of execution of the code. Also, the information provided by the annotations can be a register allocation that maps data structures of the code to registers of the second computer system. The second computer system can use such information to guide the interpreting of the code or to transform the code into a more optimized form. Other exemplary annotations can indicate that running the executable form of the code would perform an unauthorized operation at the second computer system.

Abstract: A bus configuration and associated termination for an Intel Slot 2 bus supporting communication for at least one Intel Pentium II Xeon processor. The Intel Slot 2 bus is configured in an in-line topology and includes a plurality of Intel Slot 2 bus connectors connected to the Intel Slot 2. A first plurality of bus terminators are electrically connected to a first end of the in-line Intel Slot 2 bus and a second plurality of bus terminators are electrically connected to a second end of the in-line Intel Slot 2 bus. The first and second plurality of bus terminators are constructed in accordance with termination specifications required by Intel on terminator cards which are inserted into unpopulated Intel Slot 2 bus connectors except that one end of the bus has the one hundred and fifty ohm pull-up resistor required by Intel replaced with an eighty two ohm pull-up resistor.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: An arbiter system for the instruction issue logic of a CPU has at least two encoder circuits that select instructions in an instruction queue for issue to first and second execution units, respectively, based upon the positions of the instructions within the queue and requests by the instructions for the first and/or second execution units. As a result, since the instruction can request different execution units, this system is compatible with architectures where the execution units may have different capabilities to execute different instructions, i.e., each integer execution unit may not be able to execute all of the instructions in the CPU's integer instruction set. According to the present invention, one of the encoder circuits is subordinate to the other circuit. The subordinate encoder circuit selects instructions from the instruction queue based not only on the positions of the instructions and their requests, but the instruction selection of the dominant encoder circuit.

Abstract: A manually operable ejector assembly is mounted on the front side of a carrier that supports a hot-pluggable disk drive for removable slidable insertion into a sheet metal cage structure portion of a computer system. The ejector assembly includes a main ejector lever which is pivotally spring-biased in a forward direction outwardly from the front side of the carrier, and is releasably held in a pivotally retracted position by a slide bar member that is spring-biased toward a retaining position in which it overlies a free end of the ejector lever. To remove the carrier from the cage, the slide bar member is slid away from the free ejector lever end, thereby permitting the lever to be spring-driven outwardly to an intermediate open position in which it conveniently forms a pull-handle but does not disconnect the drive from the backplane connector.

Abstract: A method and apparatus for identifying devices on a network. A management device is configured to multicast a query message to request identification of network devices. Each of the network devices is configured to respond to the management device multicast message by transmitting a reply message containing identification information of the responding device. The management device includes a directory containing the identification information of the network devices. The network protocol can include the TCP/IP protocol, and the packets have a format complying with a bootstrap protocol.