Abstract: A computer system includes a processor, a memory device, at least one expansion bus, and a bridge device coupling the processor, memory device, and expansion bus together. The bridge device preferably includes a memory controller that is capable of arbitrating among pending memory requests, and in certain situations, starting the next cycle while the current cycle is finishing. This allows executing at least two memory requests concurrently, thus improving bus utilization and retrieving and storing data in memory occurs more efficiently. The memory controller can start the next memory cycle during the current cycle when the next memory cycle will result in a page miss and a bank hit to a bank that is not associated with the most recently used (MRU) page. Further concurrent memory request execution is possible when the next cycle will be a page miss and bank miss.

Abstract: A method for controlling access to a storage element that forms a portion of a logical storage device includes setting a write-barrier value to a first value upon receiving a request to copy the contents of the logical storage device. Write operations to the storage element are prohibited with the write-barrier value set to the first value. The portions of the logical storage device associated with the storage element are then copied. Upon the completion of the copying, the write-barrier value is then set to a second value.

Abstract: A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, or as a second memory interface. The function of the multiple use chipset is determined at the time of manufacture of the computer system, or in the field whether an AGP bus bridge or a second memory interface is to be implemented. Selection of the type of bus bridge (AGP or second memory interface) in the multiple use core logic chipset may be implemented by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP device or a second memory connected to the core logic chipset.

Abstract: A card guide assembly for isolating printed circuit boards from each other during insertion and removal from a mounting array. The assembly includes first and second isolation channels that are configured to permit the receipt of a variety of PC board sizes therein and a securement cap for receipt thereover. The cap may be adjustably positioned within the isolation channels for establishing a secured mounting for a variety of PC board sizes. A locking mechanism is provided between the cap and the channels for secured engagement therebetween. The channels are mounted on opposite sides of the PC board connector region permitting conventional mounting of the PC board into a mounting connector.

Abstract: Disclosed is an object-oriented programming mechanism to control and manage object ownership by more than one reference. According to that mechanism, an envelope class is created in a manner that makes itself look (to the user) like the actual object. The envelope class is then used to create an envelope object that references the actual object, and used as a base for all other references to the actual object to which the object reference relates. The envelope object keeps track of how many references are made to the underlying object by maintaining a reference count that is incremented with each reference to the object that is established, and decremented each time a reference is deleted or goes out of scope. The object reference will keep the object viable (i.e., maintain its memory space) until the last reference to the object goes out of scope. When this happens, the envelope object will then call upon one or more virtual member functions to destroy the object and free the memory space it was using.

Abstract: A computer convergence system includes a convergence functionality module, a computer, and a display device. The convergence functionality module includes a first input for receiving a first video signal and a second input for receiving a second video signal. The computer is coupled to the convergence functionality module and receives therefrom indications of the first video signal received at the first input port and indications of said second video signal received at the second input port. The computer includes a controller for controlling the mapping of the indications of the first video signal to the primary video viewing surface, and further controls the mapping of the indications of the second video signal to either the second video viewing surface or the data acquisition destination.

Abstract: A port-centric controller system for a computer including a plurality of network ports implemented with a plurality of network controllers and a driver system capable of operating each of the network ports in either a stand-alone mode or a team mode and that monitors the status of each of the network ports. The controller system further includes configuration logic that interfaces the driver system to display port-specific graphic representations of the configuration and status of each of the plurality of network ports. The graphic representations preferably distinguish between each of the plurality of network controllers and each of the plurality of network ports. The driver system monitors the link status of each of the network ports indicative of cable status, and the graphic representations include a corresponding cable fault icon indicative of a cable fault at a network port.

Abstract: A circuit for isolating a device from a bus includes a local clock, a clock multiplexer, and control logic. The clock multiplexer has a first input terminal coupled to the local clock, a second input terminal coupled to the first clock line of the bus, a control input terminal, and an output terminal. The output terminal is adapted to provide an output clock signal to the device. The control logic is coupled to the control input of the clock multiplexer and adapted to detect a bus isolation event. The control logic is further adapted to generate a bus isolation signal in response to the bus isolation event and provide the bus isolation signal to the control input of the clock multiplexer. A method is provided for isolating a device from a bus. The method includes detecting a bus isolation event. An isolation signal is generated in response to the bus isolation event. One of a local clock signal and a first clock signal provided by the bus is selected based on the isolation signal.

Abstract: A memory system has a plurality of interleaved memory ranks that use SDRAMs requiring a periodic refresh, and an arbiter which controls access to the memory ranks and restricts access to a memory rank being refreshed. The memory ranks are interleaved on a memory module. Counting refresh registers on each memory module are associated with the module's memory ranks. The arbiter has its own counting refresh register. At regular intervals, the arbiter broadcasts a refresh signal along with a refresh address to the modules via a transaction bus. The refresh address provided by the arbiter is latched by the refresh registers which then begin counting at a pre-programmed interval. A refresh to a particular memory rank is triggered when a refresh register associated with the memory rank matches a unique identifier assigned to that rank. The arbiter uses its refresh register to identify the memory rank being refreshed, allowing the arbiter to restrict access to that memory rank.

Abstract: A system and method exclusively accesses a shared storage location using a shared algorithm. Competing processors follow the algorithm for reserving exclusive access to the shared storage location. Those competing processors that have not successfully reserved exclusive access honor the reservation of the successful processor and delay their own access attempts. Two critical storage blocks and two delay times are typically used during an attempt to reserve exclusive access for a processor.

Abstract: A new system for organizing received messages for a user does not require the user to examine and categorize each received message, and enables the user to conveniently and efficiently modify filtering rules used to define folders that organize received messages. The system includes a received information database for storing received messages. One or more message filters are provided, for example where a separate message filter is provided to handle each specific message source or message type. Each message filter generates indices corresponding to portions of the received messages it processes. The message filters store the indices into a database index such that the indices are associated with the message and message portions to which they correspond. The system includes a plurality of message folders, such that received messages are organized based on a predetermined set of message characteristics. The system stores a search query within each folder.

Abstract: An apparatus is provided for reducing read latency for an I/O device residing on a bus having a short read latency timeout period. The apparatus includes a I/O bridge on an I/O bus having a longer read latency timeout which modifies read transactions into two separate transactions, a write transaction to the same address requested by the read transaction which will force a write-back if the address hits in the CPU's write-back cache, and then performing the read transaction which is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the I/O bus having a short read latency timeout period from exceeding it's read latency timeout limit.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. CPUs, in particular, may be migrated, or reassigned, from one partition and operating system instance to another, allowing different loads in the system to be accommodated.

Abstract: A technique for reducing the height of a portable computer by reducing the effective number of housing walls across the height relates specifically to the system height over the battery slot. An enclosure of the portable computer, and specifically, a wall of the enclosure in the computer's battery slot is interwoven with a wall of the battery pack housing. The effect of the invention is that the total height of the portable computer measured through the portable computer's battery slot is reduced by the thickness of one of these walls. In one implementation, there is a reduction in the system's height of over a millimeter.

Abstract: A method and apparatus that determines and uses two nearly uniform independent hash functions. The hash functions are created using only linear arithmetic and 4-byte machine register operations and, thus, can be created very quickly.

Abstract: The invention recognizes that a probability density function for fitting a model to a complex set of data often has multiple modes, each mode representing a reasonably probable state of the model when compared with the data. Particularly, an image may require a complex sequence of analyses in order for a pattern embedded in the image to be ascertained. Computation of the probability density function of the model state involves two main stages: (1) state prediction, in which the prior probability distribution is generated from information known prior to the availability of the data, and (2) state update, in which the posterior probability distribution is formed by updating the prior distribution with information obtained from observing the data. In particular this information obtained purely from data observations can also be expressed as a probability density function, known as the likelihood function.

Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices or master devices that are designed to run master cycles on the expansion bus. The master devices couple to the expansion bus through a common expansion master interface, which executes master cycles on the expansion bus on behalf of the master devices. The South bridge also includes an internal modular master expansion bus coupling the internal master devices to the common master interface. The internal modular master expansion bus permits the master devices to run master cycles to any expansion bus by understanding a standardized group of signals represented by the internal modular master expansion (IMAX) bus.

Abstract: A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, or as a bridge between a system area network interface and the host bus and the system memory bus. The function of the multiple use chipset is determined at the time of manufacture of the computer system, or in the field whether an AGP bus bridge or a system area network interface is to be implemented. Selection of the type of bus bridge (AGP or system area network interface) in the multiple use core logic chipset may be implemented by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP device or a system area network interface connected to the core logic chipset.