Abstract: A computer method and apparatus for generating and maintaining a structured collection of documents describing a desired system is provided. A conceptual model of the desired system includes entities and relationships among the entities. An entity-relationship diagram is representative of the desired system. Documents are categorized and subsequently maintained with respect to the entities in the entity-relationship diagram. A hierarchy of process-message matrices is employed to determine the communications or dynamic exchanges of message entities in the modeled system and reflected in the entity-relationship diagram. A relational database implements the model and holds document contents (i.e., actual information) needed to automatically generate the collection of documents in a complete formatted manner for printing and/or compiling through word processing and/or compilation and linking means.

Abstract: A technique for verification of a complex integrated circuit design, such as a microprocessor, using a randomly generated test program to simulate internal events and to determine the timing of external events. The simulation proceeds in two passes. During a first pass, the randomly generated test program and data vectors are applied to a simulation model of the design being verified. During this first pass, an internal agent collects profile data about internal events such as addresses and program counter contents as they occur. During a second pass of the process, the profile data is used to generate directed external events based upon the data observed during the first pass. In this manner, the advantages of rapid test vector generation provided through random schemes is achieved at the same time that a more directed external event correlation is accomplished.

Abstract: Improved image format conversion techniques that provide improved conversion from an image format supporting transparency to an image format not supporting transparency. The techniques replace a transparency color in an original image format prior to format conversion. Consequently, the format conversion uses the replacement transparency color instead of the original transparency color, and thus is able to provide improved image conversion when converting from an image format supporting transparency to an image format not supporting transparency.

Abstract: In one aspect of the present invention, an apparatus for retaining an electrical connector is provided. The apparatus includes a tray adapted to receive an electrical device having a flexible connector coupled thereto. The tray is moveable between first and second positions. A spring extends between the tray and the flexible connector. The spring urges the flexible connector into a serpentine configuration in the first tray position.

Abstract: A method and apparatus is described for encoding a sequence of video frames at a target bit rate. A controller controls the bit r ate by providing values for a coding frame rate and quantization parameter to a frame encoder. A set of operating regions, including a first operating region and a second operating region, is defined. Each operating region includes a range of values for each parameter. These operating regions may intersect each other or be disjoint. The encoder codes the frame sequence with the value of each parameter being in the first operating region. During the coding, the controller determines to make an adjustment to the value of one parameter that would put that value out of the first operating region and in the second operating region. The controller makes the adjustment if a predetermined criterion is satisfied, otherwise the controller constrains the value of that one parameter to remain in the first operating region.

Abstract: A method and apparatus for upgrading the naming service of a distributed network data processing system uses controlled upgrades of replicated directories in clearinghouses on a node-by-node basis.

Abstract: A combination x digital subscriber line (xDSL) and analog modem including a computer bus interface, codecs, an analog front end (AFE) for xDSL communications coupled to a plain old telephone service (POTS) line and a direct access arrangement (DAA) for analog communications also coupled to the POTS line. The modem is designed on a peripheral component interconnect (PCI) card. Generally, ±12, 5 and 3.3 volts are available for PCI components. Traditionally, the AFEs for non-PCI modems were designed to operate on ±12 volts for differential POTS line driving. For differential POTS line driving, the AFE typically requires a regulated voltage. However, ±12 volts supplied to PCI cards are typically not as well regulated as the 5 and 3.3 volts, and therefore the ±12 volts is generally unsuitable for PCI modem AFE design. Furthermore, in computers that operate in different power management modes, ±12 volts may not be available to the PCI card while 5 and/or 3.

Abstract: A computer system and method using a standardized shareability scheme for establishing a shared level for each of a plurality of storage units located in the computer system. The computer system includes a plurality of hosts and controllers coupled to a peer network (storage area network). Each storage unit is coupled to one of the controllers and includes at least one parametric from a group of parametrics used in classifying the shared level of a particular storage unit. The hosts using the standardized shared levels are able to identify a shareability characteristic of each storage unit.

Abstract: A mechanism for mitigating the rate at which status reports associated with raw cell data transfers occur during receive operations in a network node is presented. The network node has an adapter for coupling a network and a host system, the host system including a host memory. The adapter operates to reassemble cell data received from the network and store the reassembled cell data in the host memory. A raw report holdoff counter is programmed to count a number corresponding to a preselected rx raw report holdoff value. If a raw cell data transfer request to be processed is detected, rx raw report information necessary to creating an rx raw cell status report is copied to a temporary storage area. When the data is transferred to the host system, the raw report holdoff counter is modified by one. When the modified counter has expired, the rx raw report information is written to a report queue in host memory.

Abstract: A dynamic proxy server (DPS) including client logic that is capable of communicating with a plurality of other server modules via corresponding internal HTTP ports, proxy logic that is capable of communicating with the other server modules via the client logic, and server logic including a communication socket. The server logic attempts to bind its socket to a master TCP port, and if successful, operates to proxy communications between the other server modules and the master port via the proxy logic. If the attempt to bind the socket to the master port is unsuccessful, the server logic binds the socket to one of a plurality of internal ports. The DPS interfaces a functional processing component (FPC) to form a dynamic processing module (DPM). In a system including a plurality of DPMs, one DPM serves as master and the other DPMs serve as secondary DPMs. Each DPM is capable of operating as master and includes watchdog logic that periodically causes the server logic to attempt to bind to the master port.

Abstract: A computer system includes a secondary bus bridge device in a portable computer and a another secondary bus bridge device in an expansion base to which the portable computer connects (docks). A peripheral in the expansion base may initiate a delayed cycle to read or write data to memory through a primary bus bridge device that also couples to a CPU. Both secondary bus bridge devices include an arbiter for controlling arbitration of a peripheral bus that connects both secondary bridge devices. The arbiter in the secondary bridge of the portable computer determines which of the arbiters will have arbitration control of the expansion bus to run cycles. When read data is available, in the case of a delayed read cycle initiated by a peripheral device in the expansion base, the primary bridge strobes a delayed cycle control signal to the arbiter in the portable computer which then gives arbitration control to the arbiter in the expansion base.

Abstract: A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid data exists within the CPU cache storage locations. If so, a writeback operation can occur. Ownership of the CPU bus is maintained by the bus interface unit during the snooping operation, as well as during writeback and the request of the memory bus by the peripheral-derived write cycle. It is not until ownership of the memory bus is granted by the memory arbiter that mastership is terminated by the bus interface unit.

Abstract: A space-saving docking station is usable to support a notebook computer docked thereto in a generally vertical, hinge-side up opened orientation on a desktop area with the computer lid display screen exposed and facing the computer user. The docking station includes a generally wedge-shaped expansion base to a front side of which the computer base housing may be electrically coupled to connect to notebook computer to desktop peripheral devices such as a keyboard and mouse, and a stand structure for supporting the expansion base, and thus the docked computer, in the space-saving vertical orientation in which the exposed notebook computer display screen is elevated relative to the desktop area and may be utilized in conjunction with the desktop keyboard and mouse.

Abstract: Apparatus, and an associated method, selects parameters determinative of video display characteristics of video displays displayable upon a video monitor. The parameters, such as brightness and contrast parameters, are stored at the video display monitor. The video display monitor is connected to a computer system unit. During booting operations, the video display parameters are retrieved by the computer system unit and selectably used to determine the video display characteristics of video displays displayable upon the video display monitor.

Abstract: A computerized method and apparatus for reducing the size of a dictionary used in a text-to-speech synthesis system are provided. In an initial phase, the method and apparatus determine if entries in the dictionary, each containing a grapheme string and a corresponding phoneme string, can be fully matched by using at least one rule set used to synthesize words to phonemic data. If the entry can be fully matched using rule processing alone, the entry is indicated to be deleted from the dictionary. In a second phase, the method and apparatus determine if the entry, considered as a root word entry, is required in the dictionary in order to support phoneme synthesis of other entries containing the root word entry, and if so, the root word entry is indicated to be saved in the dictionary.

Abstract: In a semiconductor package, a die has electrical circuits formed on a first side surface. A lead frame for connecting the electrical circuits to a power source is connected to the electrical circuits of the die. A package body made of a dielectric material is formed around the die and the lead frame. One or more fins made of a thermally conductive material are independently attached to the die by a thermally conductive bond. The fins, receive heat directly from the die, and dissipate the heat by radiative or convection cooling into the surrounding environment.

Abstract: A computer system comprising a display monitor including an audio function and a computer coupled to the display monitor including a computer controller for controlling the audio function in the monitor. The computer is operable in a computer mode, a television mode, and a combination computer/television mode for displaying computer and television information on the monitor. The system determines whether the monitor includes a controller for controlling its audio function. Based upon this determination, the system controls the audio function with the audio controller in the monitor if the monitor includes such a controller or, alternatively, with the computer controller if the monitor does not have such a controller.

Abstract: A mechanism optimizes the generation of a commit-signal by control logic of the multiprocessor system in response to a memory reference operation issued by a processor to a local node of a multiprocessor system having a hierarchical switch for interconnecting a plurality of nodes. The mechanism generally comprises a structure that indicates whether the memory reference operation affects other processors of other nodes of the multiprocessor system. An ordering point of the local node generates an optimized commit-signal when the structure indicates that the memory reference operation does not affect the other processors.

Abstract: A computer system including a memory controller provides a series of queues between a processor and a peripheral component interconnect (PCI) bus and a memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A write posting queue for processor to PCI writes must be flushed before a PCI device can access memory. If the queue is not empty when the PCI device requests a memory read, the PCI device is forced to retry the operation while the write posting queue is flushed. Also, while the queue is flushed, the processor is prevented from further posting to the queue. A timer provides a further temporary time that the processor is precluded from posting to allow enough time for the PCI master to retry the operation.