Abstract: Disclosed is a method of validating the contents of a real-time clock in a digital circuit. A plurality of memory elements create a first random signature value when power is newly applied to a circuit. The plurality of memory elements maintain the first random signature value while power to the circuit is maintained. The first random signature value is stored as a reference value such that the reference value is not altered by a power interruption. When power to the circuit is lost and then regained, a second random signature value is created. The second random signature value likely will no longer match the reference value because both the reference value and the second signature are random. When the reference value does not match the signature value, the real-time clock value is considered invalid. User input may be employed to correct the real-time clock value.

Abstract: There is provided a demodulator system comprising a first input to receive a first analog signal at a first rate; a second input to receive a second analog signal at the first rate; a MUX coupled to the first input and the second input to receive the first analog signal and the second analog signal, and to multiplex the first analog signal and the second analog signal to generate a multiplexed analog output; an ADC to receive the multiplexed analog output and generate a multiplexed digital output, the ADC operating at a second rate, the second rate substantially equal to the first rate multiplied by a total number of input analog signals; a DEMUX to receive the multiplexed digital output and generate a first digital output having a first bitstream and a second digital output having a second bitstream corresponding to the first analog signal and the second analog signal.

Abstract: Systems and methods for implementing a temperature compensated two-stage ring oscillator are described. At least one embodiment includes a system for generating a clock signal comprising a self-starting oscillator comprising two delay stages in a ring configuration. The two-stage ring oscillator is configured to generate the clock signal, wherein the delay stages are configured such that the two-stage ring oscillator has a single right-half plane (RHP) pole in each of the two delay stages where feedback is always positive. For some embodiments, the system further comprises a compensation module configured to sense temperature and process variations and adjust a supply voltage for the two-stage ring oscillator to compensate for temperature and process variations in order to maintain a constant frequency clock signal. For such embodiments, the compensation module comprises a replica circuit configured to mirror operation of the n-channel devices within the two-stage ring oscillator.

Abstract: A system for determining an optimal sampling phase is provided. The system includes a plurality of analog to digital converters, each receiving an analog signal and a clock phase signal and generating an output. A clock generator receives a reference clock and generates a plurality of clock phase signals. A sampling phase system receives the plurality of outputs of the analog to digital converters and generates an optimal sampling phase.

Abstract: Disclosed are various embodiments for determining a state of loop termination. One embodiment comprises receiving an un-calibrated echo signal for the loop under test using frequency domain reflectometry single-ended line testing (FDR-SELT) and determining the state of loop termination based on phase of the un-calibrated echo signal. The step of determining the state of loop termination comprises determining whether the loop is terminated by an open termination or a short termination by correlating the phase of the echo signal with an expected phase of the echo signal derived from measurements taken at the same loop length for open and short terminations. For other embodiments, the amplitude of the un-calibrated echo signal is analyzed to determine whether the loop is terminated by a matched-impedance termination.

Abstract: Impulse noise from nearby or intense electrical sources can disrupt communications over digital subscriber lines (DSL). The characterization of the nature, timing and length of impulse noise sources present on a DSL loop is a critical first step in mitigating the effect of impulse noise on DSL communications. DSL standards provide histograms for impulse length and inter-arrival time of impulses. These histograms can be used to derive the nature, maximum frequency and other statistics related to impulse noise on a DSL line.

Abstract: The topology of a digital subscriber line loop can play an important role in provisioning service. For example, knowledge of certain topological features in a loop can enable telecommunications companies to make better decisions about the kinds of services that can be provisioned on that loop. Additionally, knowledge of those topological features can also assist field engineers in troubleshooting problems in the field. A topology recognition engine can provide key topological features such as the loop length, presence of single and multiple bridge taps and the length of single bridge taps on a loop.

Abstract: According to an exemplary embodiment, a semiconductor structure includes an NFET situated over a substrate. The semiconductor structure further includes a P+ substrate tie ring surrounded the NFET. The P+ substrate tie ring includes a salicide layer situated on a P+ diffusion region. The semiconductor structure further includes an N well ring situated between the NFET and the P+ substrate tie ring, where the N well ring increases snap-back conduction uniformity in the NFET. The semiconductor structure further includes an N+ active ring situated between the NFET and the P+ substrate tie ring, where the N+ active ring surrounds the NFET and connects the P+ substrate tie ring to the N well ring. The N+ active ring includes a salicide layer situated on an N+ diffusion region, where the salicide layer of the N+ active ring connects the N well ring to the P+ substrate tie ring.

Abstract: The present invention solves the problem set forth above by providing a method for accelerating the production of a standalone copy of a document by a peripheral device. The invention employs a white space map of the document to be copied. The map is generated by the ASIC chip and is used by the device to identify areas of the outputted copy that do not require ink or toner. This reduces the processing resources necessary to print the copy, thus speeding up copy production.

Abstract: A method is described for performing frame synchronization that comprises performing a first synchronization to determine approximate timing of a frame boundary associated with a received signal. The method further comprises estimating frequency offset and symbol boundaries within the frame boundary based on the approximate timing and performing a second synchronization based on the frame boundary and the symbol boundary.

Abstract: A satellite signal demodulator is configured to use frequency-based channel scanning to sense the presence of a channel and to obtain the frequency profile of the channel. Once the channel is identified and the profile is obtained, channel extraction is used to identify the frequency parameters for a given channel. A coarse parameter estimation is performed to obtain a coarse estimate of the symbol rate (SR) and the center frequency (fc) of the channel. The coarse estimation can then be followed by a fine estimation of the symbol rate and center frequency (fc), using a bit tracking loop (BTL) lock indicator.

Abstract: Presently disclosed is method and apparatus for generating a random bit stream by generating a random bit according to a polynomial expression, providing a modification function operative on the polynomial expression, and modifying the polynomial expression by modifying the modification function.

Abstract: In accordance with some embodiments, a communication system is described that comprises a soft-output detector configured to receive a transmit signal and output reliability information regarding the received signal. In accordance with such embodiments, the detector comprises a symbol combiner configured to operate in both a repetition mode and a non-repetition mode, wherein repetition mode comprises receiving a plurality of signals for the transmit signal.

Abstract: Disclosed herein are systems and methods of combined Bluetooth and WLAN signaling. Such systems and methods may use a Bluetooth connection to signal WLAN capabilities and to exchange WLAN security keys. Once the file transfer has started, the actual data may be transmitted over the WLAN connection rather than over the Bluetooth connection. The WLAN connection may have a much higher throughput than the Bluetooth connection, and WLAN capability has increasingly become present inside Bluetooth enabled devices. The Bluetooth connection may be used as a control channel, while the WLAN connection may be used for data transfer.

Abstract: Systems and methods for characterizing loops based on single-ended line test (SELT) are described. One embodiment includes a method for determining whether a straight-loop departure condition exists on a loop under test. In accordance with such embodiments, the method comprises receiving an un-calibrated echo signal for the loop under test using frequency domain reflectometry single-ended line testing (FDR-SELT), a region associated with the loop under test, a platform type, and a length of the loop under test. Based on the region, platform type, and loop length, the method further comprises determining whether the loop is not a straight loop, wherein determining whether the loop is not a straight loop comprises determining whether at least one differentiating feature is present in the un-calibrated echo signal. Another embodiment includes a method for determining a loop gauge for a loop under test.

Abstract: A processor is provided that includes a primary memory and color conversion logic. The primary memory may store a first color look-up table (LUT) related to a second color space. The color conversion logic, in response to a received set of pixels having color values in a first color space, converts the received set of pixels to a second color space. The color conversion logic selectively accesses, based on a comparison of one or more pixel parameters to a threshold, one of the primary memory and a secondary memory located on a second device to obtain a color value of the second color space that is associated with each pixel of the set of pixels. The color conversion logic monitors the number of times that each of the primary memory and the secondary memory are accessed and automatically adjusts the threshold to maintain an access ratio.

Abstract: Included are embodiments for utilizing a scanning threshold. More specifically, one embodiment of a method includes entering a standby mode, wherein in the standby mode, at least one component of a communications device is shutdown, and wherein in the standby mode, at least one channel is scanned to determine potential interference and monitoring exchanged traffic with the communications device. Some embodiments include determining a relative volume of the exchanged traffic, compared to a predetermined threshold and based on the determination of the relative volume of the exchanged traffic and the predetermined threshold, entering a power save standby mode, wherein in the power save standby mode, scanning of the at least one channel is terminated.

Abstract: Systems and methods for providing bias currents to multiple analog circuits are disclosed. An integrated circuit comprises a calibration circuit which compares a high tolerance external component to a plurality of internal components manufactured to span the variability of the process, voltage and temperature. The best fitting internal component is communicated to bias circuits which can select an internal component from a local plurality of internal components with matching desired characteristics. In this manner, analog circuits can be locally biased with the tolerance usually associated with a high tolerance external reference component, without the necessity for a local external reference component.

Abstract: Systems and methods for reducing the peak-to-average ratio (PAR) at the transmitter can reduce the dynamic range required in various analog components. PAR can be reduced by applying a time-domain compensation signal which reduces the magnitude of peaks in the time-domain signal prior to transmission where the time-domain compensation signals use tones that are reserved for the purpose of reducing the PAR. The reservation of these reserved tones for PAR can be implemented by altering the typical startup procedures in a digital subscriber line (xDSL) system. The use of the reserved tones to reduce the PAR can be implemented using a low complexity algorithm or using an adaptive technique.

Abstract: Systems and methods for reducing the peak-to-average ratio (PAR) at the transmitter can reduce the dynamic range required in various analog components. PAR can be reduced by applying a time-domain compensation signal which reduces the magnitude of peaks in the time-domain signal prior to transmission where the time-domain compensation signals use tones that are reserved for the purpose of reducing the PAR. The reservation of these reserved tones for PAR can be implemented by altering the typical startup procedures in a digital subscriber line (xDSL) system. The use of the reserved tones to reduce the PAR can be implemented using a low complexity algorithm or using an adaptive technique.