Abstract: Self-administered survey devices include a display, an input device, a memory and a control device which controls the display to show at least one survey question and control the memory to store a response to the at least one question. A system and method for carrying out self-administered surveys utilize a centralized survey data processor and a plurality of self-administered survey devices for storing survey data entered by respective respondents and wherein survey data is wirelessly transmitted from the plurality of self-administered survey devices to the centralized survey data processor.

Abstract: A meter for unobtrusively monitoring the tuning of a home entertainment center. The device is able to work with remote controls of components of the center. The present invention receives signals from the remote control(s), decides to which component the signal was intended, sends an infrared signal to the proper component, and stores tuning information regarding the center. The stored information may be retrieved at a later time and used to make programming decisions. The present invention includes infrared sensors which receive the signals from the remote(s), a microprocessor, and a transmission device to transmit the signal to the intended device. Alternately, the control signal may be generated by a touch panel array placed over digital keypads of the center's components. When a key is pushed, the control signal is generated. The touch panel array(s) can serve solely or in combination with the remote control(s) to generate control signals.

Abstract: A scan diagnostics apparatus and method is useful in connection with the memory integrated circuit. A shift register is provided which can receive data in parallel from the input register and output the data serially. The shift register can receive serial data and output in parallel either to the input buffer or the output buffer. Preferably the shift register can receive in parallel, data from the output buffer and output the data serially.

Abstract: A radiation hardened or fail safe circuit is coupled between a peripheral data storage device, for example a disk drive, and its associated controller. The circuit includes an AND logic gate with two inputs: a write enable signal from the controller; and a sensing input logic signal normally high, but driven low responsive to the sensing of unacceptably high levels of radiation. A delay means is interposed between the controller and the AND gate, for delaying propagation of the write enable signal a sufficient amount of time to ensure that the sensing input to the AND gate responds to the detection of high radiation before the arrival of the write enable signal. The delay means can be an LC delay circuit, a coaxial cable, or a series of latches clocked in alternation order by opposite phases of an oscillator.

Abstract: A method for designing integrated circuits for improved testability. A main logic function operable in initialization and test modes is defined in terms of component logic macros. Testability circuitry for generating CLEAR, CLEAR0 and CLEAR1 testability signals is also defined. The CLEAR signals have the first logic state during system operation in the initialization mode, and first and second logic states equal amounts of time during the test mode. The CLEAR0 signals have the first logic state during the initialization mode, and have the second logic state most of the time and the first logic state the remainder of the time during the test mode. The CLEAR1 signals have the first logic state during the initialization mode, and have the first logic state most of the time and the second logic state the remainder of the time during the test mode. First-type macros, such as multiplexers having Select or other inputs requiring CLEAR signals during the test mode, are identified.

Abstract: The disclosure relates to an apparatus and method for creating digital signatures from frames of selected video segments such as TV commercials by a digitizing, compression and selection process which produces a multi-digit signature from each frame. The signatures are stored in a memory database. In the recognition mode broadcast video transmissions are similarly digitized frame by frame to generate signatures which are then compared with the signatures in the database to find matches. The system cycles efficiently through the database testing for signature matches and then totalizing the signature matches to determine occurrences of a match between a transmitted segment or commercial and a stored segment or commercial. The system also includes signature generating and comparison circuits which permit wide variations in the quality of the input video signals form a variety of different media sources such as off-air, videotape or camera inputs while maintaining accurate recognition.

Abstract: Data messages are transmitted between host data processors and a communications processor. Data messages from a communications processor are transformed for the host processor to which the message is assigned. Data messages from a host processor are transformed for the communications processor. Protocol is established between (a) untransformed data messages from the communications processor and transformed data messages for the communications processor, and (b) untransformed data messages from each host processor and transformed data messages for each host processor. A device interface connects a plurality of host processors to a plurality of buses, each bus being connected to one communications processor. The device interface handles the protocol, transformation and control function in parallel so that messages between a given host processor and terminal connected to a communications processor are processed through a device interface.

Abstract: It is known to use a miss information holding register in a cache memory organization to store the details of a CPU load request on a cache miss so that the cache may accept subsequent requests pending the receipt of data in respect of the first request. In the subject invention, this organization is modified for use with a virtual addressable cache memory by incrementing a counter which overflows to free the miss information holding register with each untranslatable response signal from the address translation unit relating to the request stored in the miss information holding register. The modified organization also clears the used bit associated with the location in the cache tag memory to which the tag addresses of the request has been stored upon receipt of the first untranslatable response signal from the address translation unit in respect of the request.

Abstract: An assembly is disclosed for releasably mounting a semiconductor package with respect to a rigid carrier, in a predetermined alignment with the carrier to protect the package leads and position the leads for electrical testing. Two substantially identical dielectric frames are positioned on opposite sides of the leads and fastened in a sandwich arrangement enclosing remote end portions of the leads. Registration openings, provided at opposed corners of the frames, receive registration pins projected from the carrier, thus to positionally align the package and carrier in transverse directions. Spring-loaded retainers engage a central body of the semiconductor package to retain the package against longitudinal movement relative to the carrier.

Abstract: Apparatus in an automatic telecommunications system which communicates between a central location and at least one remote location over the switched telephone network, senses changes in loading of the telephone line which correspond to a telephone going off-hook, to serve as an indication that a telephone has gone off-hook and to cause the automatic telecommunications system to relinquish its use of the telephone line, or not to go off-hook if a telephone is in use.

Abstract: An overflow prediction scheme is provided to operate in parallel with an integer multiply within a computer to predict overflow conditions of the resultant register. The operands to be multiplied are examined to determine the position of the most significant bit. The position values are summed to determine a minimum resultant size. If the minimum resultant size exceeds the size of the data field of the resultant register, an overflow flag is set. If the minimum resultant size is less than the size of the resultant register data field, the overflow flag is not set. When the minimum resultant size equals the size of the resultant register data field, the setting of the overflow flag will depend on the signs of the expected and actual resultant.

Abstract: A logic chip contains a plurality of ranks of flip-flops with combinational logic elements connected in between the flip-flop ranks. Each flip-flop has at least two distinct data paths. The first path is for the normal passage of data to combinational logic units following the rank of flip-flops, and the second path is a test path which is connected directly with the next rank of flip-flops. Operands may be shifted in parallel to bypass combinational logic units and may be directed to selected combinational logic for test purposes. The flip-flops in a rank may be serially scanned or operate in parallel to send specific operands through selected combinational logic units. It is adaptable to custom or semi-custom VLSI chip design and it teaches that any "component" (for example, a logic unit or a single element) may be tested individually using two data paths (one for test and one for operation or normal data).

Abstract: An apparatus for simultaneously testing multiple integrated circuits includes a sensing circuit associated with each of the tested circuits. Each sensing circuit includes a differential amplifier with its positive input connected to the input of the test circuit, and its inversion input connected to the test circuit output. The test circuit input and positive amplifier input are biased to a selected voltage, and the voltage drop across the test circuit is provided to the amplifier inversion input. Whenever the test circuit is open, intermittently open or highly resistive, the voltage drop across the test circuit exceeds the threshold voltage of the differential amplifier, causing the amplifier to generate a high level logic output representing an open circuit condition. The outputs of the various sensing circuits together form a digital word representative of the condition of all of the test circuits.

Abstract: Linear interpolation is applied to each pair of placement coordinates in a data driven surface mount component placement robot in order to eliminate component misplacement due to board artwork dimensional inaccuracies. The linear interpolation algorithm is derived by measuring the actual dimensions of the artwork of a given board by an integrated vision system via a camera attached to the robot arm.

Abstract: This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.

Abstract: A system is disclosed which may be used for collecting television channel tuning data, household purchase data, VCR channel usage data and the like; on site at a plurality of preselected households, wherein the system concentrates and transmits the collected data to a central site in a fault tolerant manner, transparent to the occupants of the household. The novel system features a hub and spoke architecture for effecting communications between the central site and each household (remote site). The hub and spoke architecture at each remote site comprises a hub unit, and a set of spoke meters. The hub unit is adapted to be coupled, in a variety of ways, to a set of metering devices, one or more of which is coupled to one or more television receivers and/or cable television converters. Not all of the metering devices need be coupled to the television receiver or cable converter, e.g., stand alone purchase meters and wands may be coupled to the hub. The meters may be polled systematically, e.g.

Abstract: An apparatus and method for a cleaning process control is disclosed. The apparatus includes a printed wire circuit board that is made on a Pyrex glass or other transparent substrate. Components are attached to the printed wire circuit board and then the circuit card assembly which is formed is cleaned using a selected cleaning process. The circuit card assembly can then be inspected to determine the effectiveness of a particular cleaning process by flipping over the transparent circuit card, peering through the substrate to inspect for corrosion and solder balls. The circuit card assembly can then be cleaned more extensively and used again to check a different cleaning process.

Abstract: A metal heat spreading cup, hereinafter referred to as a "conductive cup module" ("CCM"), is utilized as part of the interface between at least one semiconductor being cooled and a pedestal, sometimes referred to as a "boss", coupled to a cooling medium. The semiconductor being cooled is, according to one embodiment of the invention, bonded to the underside of the cup. Furthermore, according to the invention, the pedestal is inserted into the cup and is bonded thereto by use of a deformable thermal conductive compound, (such as a thermal paste or grease) also inserted into and contained within the cup. The compound spreads upon being displaced by the inserted pedestal. The compound remains deformable during operation of the cooling system.

Abstract: Disclosed is a Runout Velocity and Acceleration tester which converts an analog acceleration signal to a digital signal. The individual bits of digital data are then transformed into an exponential function. The exponential function that results is then solved for the worst case acceleration on a surface.

Abstract: A data communications apparatus transfers data between two channels, the data formats of each being incompatible with the other. Index registers receive index addresses from each channel to access a pointer in a pointer RAM. The pointer addresses a data location in a data RAM to permit data to be stored or read from either channel at the data transfer rate and byte size for that channel. Registers are provided between each RAM and at least one of the channels to concatenate smaller byte words for transfer between the RAMs and the one channel. Counter apparatus drives the pointer RAM to access successive locations in the data RAM, as desired.