Abstract: A graphics accelerator chip which interprets instructions and data transferred from a microprocessor via an external data bus logically coupled to the microprocessor. A host logic interface buffers the information received from the microprocessor with an on-chip first-in first-out (FIFO) memory which has an address space mapped onto a contiguous sequential address space of the microprocessor. A state machine having a temporary memory receives and interprets instructions and data from the FIFO memory, and routes them to a graphics register set which performs logical graphics operations based upon the graphics instructions and data. The temporary memory stores the last primitive command received, allowing the chip to perform multiple graphics operations where a primitive command is received from the microprocessor only once. A separate data bus from the host logic interface to the graphics register set enables direct access to the graphics registers from the microprocessor.

Abstract: A mounting system, for supporting semiconductor process gas delivery and control components for assembly and use as a gas stick, aligns the connection union seals between fittings on adjacent components to absorb accumulated stresses resulting from manufacturing tolerances and reduce the likelihood of seal leakage. Components are mounted on individual upper clamp members which are secured to lower clamp members to form a slidable but non-rotatable radially aligned yoke around a rigid elongate support member for subsequent longitudinal positioning and joining of adjacent fittings.

Abstract: A locking device for preventing relative rotation of pretorqued compression nuts used in face seal mechanical fittings includes an inner member having a cavity sized to slide onto and non-rotatably enclose the male or first nut of the fitting, an outer member having a first cavity sized to rotatably receive the inner member and a second cavity sized to slide onto and non-rotatably enclose the female or second nut of the fitting, and at least one set screw projecting inwardly through a threaded borehole in the outer member to non-rotatably engage and lock the inner member.

Abstract: A shielded housing for a computer or the like including top and bottom housing parts. The top housing part includes a top wall and two side walls. The bottom housing part includes bottom, front and back walls. An inverted V-shaped channel is carried by the side walls adjacent the lower edges for a cooperating fit between the channels and upturned flanges carried by the bottom wall planar surface. The inner surfaces of the housing parts include shielding for reduction of electrostatic noise from the enclosure. The cooperating fit between the channels and bottom wall flanges provide and improved side wall junction to prevent electrostatic noise from leaking along the side wall edges.

Abstract: A method and apparatus for implementing the same are provided for digitally synchronizing the timing of a sequence of electrical output pulses in accordance with a selectable, permissably non-linear function of the timing of a sequence of electrical input pulses. The method and apparatus are illustrated with reference to application thereof to overcoming the problem of degradation of synchronization caused by so-called "peak shift" due to the adjacent data effect in the reading of binary data stored on magnetic disks or the like. Pulses of a timing reference signal having a uniform interval equal to a sub-multiple of the normal average interval of the desired output pulses are continuously counted to a number base equal to the denominator of said sub-multiple, and output pulses are produced whenever a pre-selected count value occurs. Output pulse timing correction values in accordance with the synchronizing function selected are stored in memory.