Abstract: There is disclosed a shared multiprocessing system with several nodes, or processing units, interconnected together for communication purposes by a dual channeled crossbar switch. Several such multichannel crossbar switches can be linked together to form a large cohesive processing system where processing units from one node can access memory from another node on the same crossbar or from another node on a different crossbar. The interconnection between crossbars is accomplished by a circular ring. In operation, the system allows for long memory latencies while not increasing the length of short (local) memory latencies. This is accomplished by storing the bulk of long latency requests at the local processing unit and only sending the request when there is an actual availability of communication capacity to handle the long latency request.

Abstract: A distributed memory I/O interface 10 is provided which allows a plurality of standard peripheral bus I/O controllers 101 to perform multiple transfer operations simultaneously and independently within a networked, distributed memory system 102. The interface 10 includes a peripheral interface 11 to the I/O controllers 101, a memory interface 12 to the distributed memory system 102, a system interface 13 to the processors of the distributed memory system 102, a caching circular buffer RAM 12, and an internal bus 105. The operations of the interface 10 are controlled by logical channels. Each logical channel comprises a channel context, which includes a set of parameters stored in buffer RAM 12 that specify among other things logical address space, a physical memory map, a RAM buffer segment, and a set of allowed transactions for use during channel operations.

Abstract: A processing system 100 is provided which includes first and second hypernodes 101, each of the hypernodes 101 having at least first and second coherent interfaces 106. At least first and second interconnect network 107 are provided, the first network 107 coupling the first interfaces 106 of the first and second hypernodes 101 and the second interconnect network 107 coupling the second interfaces 106 of the first and second hypernodes 101.

Abstract: Circuitry 300 is disclosed for isolating faults in a path 304 transmitting data words each having at least one data bit and at least one parity bit. Circuitry 300 includes a plurality of exclusive-OR gates 303 each having a first input coupled to the data path 304 for receiving a bit of a one of the data words being transmitted along path 304. A plurality of multiplexers 305 are also provided, each multiplexer 305 including a first input coupled to an output of a corresponding one of the exclusive-OR gates 303 and a control signal input for receiving a control signal. A plurality of registers 306 have an input coupled to an output of a corresponding one of the multiplexers 305 and an output coupled to a second input of a corresponding one of the exclusive-OR gates 303 and a second input of the corresponding one of the multiplexers 305.

Abstract: Disclosed are systems and methods for protecting a software program from unauthorized use and copying through the removal at least one of a plurality of instructions comprising a software program, and encrypting the removed instruction utilizing an encryption algorithm to produce an encrypted instruction, the encryption algorithm responsive to a randomly generated key.

Abstract: Scanning circuitry 300 is provided which includes first input circuitry 302 which is operable to transfer bits of received data in response to a first clock signal. Second input circuitry 303 is also provided which is operable to transfer the bits of received data in response to a second clock signal. At least one first storage device 307 is provided which is operable to transfer bits of data received from the first input circuitry 302 in response to the first clock signal. At least one second storage device 308 is provided which is operable to transfer bits of data received from the second input circuitry 303 in response to the second clock signal. First output circuitry 309 is provided which is operable to transfer bits of data received from the at least one first storage device 307 in response to the second clock signal. Further, second output circuitry 310 is provided which shifts bits of data received from the at least one second storage device 308 in response to the second clock signal.

Abstract: An electrical assembly 100 is provided which includes a land grid array integrated circuit package 103, a socket 104, a printed circuit board 106 and a clamping lid 101. Socket 104 and clamping lid 101 have major surface dimensions no greater than the major surface dimensions of the LGA integrated circuit package 103 in order to limit board space requirements to the minimum required by the circuit package 103. Alignment means associated with integrated circuit package 103, socket 104 and printed circuit board 106 are provided to maintain alignment between contact pads 120 on circuit package 103 and first ends of compressible conductors 111 on socket 104 and between contact pads 122 on circuit board 106 and second ends of compressible conductors 111. In the completed assembly, clamping lid 101 applies pressure to an adjacent surface of integrated circuit package 103 thereby compressing compressible conductors 111 against contact pads 120 and contact pads 122.

Abstract: A heat transfer assembly 11 is disclosed for transferring heat from a heat generating electronic device 15 or computer chip to ambient air. The heat transfer assembly 11 is comprised of a heat pipe 20 mounted perpendicular to a heat generating electronic device 15. The heat transfer assembly 11 is designed to provide a mechanically solid support for the bonding of the various heat transfer assembly components and to use circumferentially mounted fins 23 to increase the efficiency of heat transfer away from the electronic devices 15. The heat transfer assembly can function effectively when mounted in any direction. Thermocouples 42 are used to monitor the temperature and efficiency of the heat generating electronic device 15 such that corrective action can be initiated if the device begins to overheat.

Abstract: A circuit is disclosed for reducing the number of signal lines passing through a connector (205) comprised of a shift register coupled to a plurality of input data lines and half as many output data lines. When a load signal is received, the shift register latches the data from the input data lines and immediately transmits half of the data to the output data lines and through the connector. When the shift register receives a shift signal, the other half of the data is shifted onto the same output lines and pass through the connector to achieve a two-to-one multiplexing function.

Abstract: Disclosed is an apparatus and method for delivering power utilizing a multiplane power via matrix wherein the vias are each interconnected on each of the planes through which they pass such that a current flowing along any particular via, or via group, is free to either continue along its current path, or to move across any of the planes as a function of least resistance. The invention provides a system of vias for transferring power from any particular first plane to any desired second plane.

Abstract: Debugging of computer programs is necessary for the development of the programs as well as for maintaining the operation of the programs. Symbolic debugging requires the ability to relate the current position in the object code program to the corresponding position in the source code. In the absence of compiler optimization, correlating the source and object code elements is a straightforward procedure. However, when the object code has been optimized, the relation between the source code constructs and object code instructions can become convoluted and complex. A correlation technique for optimized code is disclosed which maps the source constructs (source units) through each of the optimization operations by use of compilation nodes and associated source units to build a table which relates ranges of object instructions to the source units which produced the object instructions.

Abstract: An error correcting code and apparatus are used in conjunction with a main memory in which a data word is stored in a plurality of circuits each of which produces multiple outputs. A minimum number of check bits are stored together with the data word for detecting and correcting single bit errors and detecting the existence of multi-bit errors. A parity bit for the entire data word is also stored. For a 32-bit data word, at least 3 bits of the data word are stored in each of 10 memory circuits. Seven check bits and one parity bit are also stored in the 10 memory circuits wherein no more than one of the check bits or parity bit is stored in any one memory circuit. Upon reading the data word from the memory a set of verify check bits and a verify parity bit are generated and compared to the stored check bits and stored parity bit to produce a check bit syndrome and a parity bit syndrome.

Abstract: A computer system having a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single processor, but when a parallelization instruction is encountered, which indicates that code can be executed in parallel, a semaphore is posted to invite other processors to join in parallel execution of the process. If any other processors in the system are idle, those processors detect the semaphore and accept a thread of process operation. Two or more processors may join in parallel operation if sufficient operations are available.

Abstract: An interlock for a disk drive unit having a handle and a camming arrangement responsive to pivotal movements for inserting and withdrawing the unit from a housing fixture. A solenoid is actuable to lock the handle when the unit is fully inserted. A sensor is adapted for sensing an interlock engagement between the solenoid armature and the handle. For removing the disk drive unit, a delay is interposed before retracting the solenoid armature to assure that the disk drive unit is fully stopped before the handle can be rotated for removal of the unit.

Abstract: A computer system comprises a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single processor, but when a parallelization instruction is encountered, which indicates that code can be executed in parallel, a semaphore is posted to invite other processors to join in parallel execution of the process. If any other processors in the system are idle, those processors detect the semaphore and accept a thread of process operation. Two or more processors may join in parallel operation if sufficient operations are available.

Abstract: A physical cache unit (100) is used within a computer (20). The computer (20) further includes a main memory (99) a memory control unit (22), inputs/output processors (54, 68) and a central processor (156). The central processor includes an address translation unit (118), an instruction processing unit (126), an address scalar unit (142), a vector control unit (144) and vector processing units (148, 150). The physical cache unit (100) stores operands in a data cache (180), the operands for delivery to and receipt from the control processor (156). Addresses for requested operands are received from the central processor (156) and are examined concurrently during one clock cycle in tag stores (190 and 192). The tag stores (190 and 192) produce tags which are compared in comparators (198 and 200) to the tag of physical addresses received from the central processor (156).

Abstract: A vector processing computer (20) includes a memory control unit (22), main memory (99), a central processor (156), a service processing unit (42) and a plurality of input/output processors (54, 68). The central processor (156) includes a physical cache unit (100), an address translation unit (118), an instruction processing unit (126), an address scalar unit (142), a vector control unit (144), an odd pipe vector processing unit (148) and an even pipe vector processing unit (150). Vector elements are transmitted from memory, either main memory (99), a physical cache unit (100) or a logical cache (326) through a source bus (114) where the elements are alternately loaded into the vector processing units (148, 150). The resulting vectors are transmitted through a destination bus (114) to either the physical cache unit (100), the main memory (99), the logical cache (326) or to an input/output processor (54).

Abstract: The computer (10) includes a memory control unit (12), a central processing unit (14) and a memory array unit (16). A plurality of memory array planes (36, 38, 40 and 42) are included within the memory array unit (16). A latch (82) receives write data from the memory control unit (12) through a bus (26). Address and control information is transferred from the memory control unit (12) to timing and address circuits (28, 30, 32, 34). The write data is transferred from the latch (82) into a selected one of the memory array planes (36, 38, 40, 42). For each of the memory array planes (36, 38, 40, 42) there is provided a respective read latch (60, 62, 64, 66) for receiving read data. The ouputs of the memory array planes are not connected in common. The ouputs to read latches (60, 62, 64,66) are connected in common through a bus (76) for transferring read data through the data bus (26) back to the memory control unit (12).

Abstract: A computer (20) is configured for optimizing the processing rate of instructions and the throughput of data. The computer (20) includes a main memory (99), a memory control unit (22), a physical cache unit (100), and a central processor (156). A instruction processing unit (126) is included within the central processor (156). The function of the instruction processing unit (126) is to decode instructions and produce instruction execution commands or directing the execution of the instructions within the central processor (156). Instructions are transferred from the main memory (99) into a register (180) where the address fields of the instructions are decoded to produce a cracked instruction and these instructions are stored in a logical instruction cache (210). As the cracked instructions are selected they are transferred to an output buffer and decoder (214) where the remaining fields of the instructions are decoded to produce instruction execution commands.

Abstract: A communication bus (14) provides bidirectional data communication between a computer (12) and various peripheral units including input/output processors (18, 20) and a service processor (22). The computer includes a memory control unit (24) which is connected to a memory array (26). A central processor unit (30) is connected for data exchange with the memory control unit (24). Data blocks are transferred through the bus (14) and either originate or terminate at the memory array (26). A peripheral unit, such as the processor (18) transfers a data block by first transferring a header parcel (146) which defines an address, block length and type of function. This is transmitted to the memory control unit (24) which carries out the desired data transfer by sending or receiving sequential data parcels. An interrupt bus (16) connects each of the units of the computer system (10) including the processors (18, 20, 22) and the central processing unit (30).