Abstract: A computer includes a memory for storing the machine instructions therein and an arithmetic logic unit for carrying out logical and arithmetic operations. An instruction processing unit is provided for receiving and decoding machine instructions which are received from the memory. The instruction processing unit produces an entry address for the first microinstruction which corresponds to the machine instruction which was decoded by the instruction processing unit. A dispatch control store is connected to receive the entry address and further has stored therein the first microinstruction for each of the machine instructions. The dispatch control store produces a selected one of the microinstructions stored therein upon receipt of the entry address. A main control store is provided for storing therein all of the microinstructions for each of the machine instructions other than the first microinstruction for each of the machine instructions.

Abstract: An operand processing unit (10) carries out processing of operands in a computer. The unit (10) includes a plurality of operation circuits (12, 14, 16, 18, 20). A source bus (22) provides one operand per clock cycle to the operation circuits (12, 14, 16, 18, 20). A destination bus (24) receives one resultant per clock cycle from the operation circuits (12, 14, 16, 18, 20). Within each operation circuit there is provided an operand processing circuit (80) which performs a selected function with the received operands. These functions include, for example, multiplication, division, addition, subtraction, logical AND, and shift. Logical circuitry provides a priority assignment to the operation circuits (12, 14, 16, 18, 20) for sequencing the loading of operands into the highest priority operation circuit (12, 14, 16, 18, 20) which is not busy processing operands within its corresponding operand processing circuit (80).