Patents Assigned to CoorsTek KK
  • Patent number: 10674566
    Abstract: Provided is a planar heater in which a carbon wire heat generator is housed in along quartz glass housing portion, and the planar heater suppresses disconnection of the carbon wire heat generator by limiting a contact region between the carbon wire heat generator and the long housing portion, and capable of efficient radiation heating. In the planar heater, the plurality of long housing portions is disposed on the same plane, and heat is generated by energizing the carbon wire heat generator, each of the plurality of long housing portions is formed in a polygonal circular arc shape in which a plurality of linear portions is connected at a bent portion, respectively, and the plurality of long housing portions is disposed along the circumferences of a plurality of concentric circles.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 2, 2020
    Assignee: COORSTEK KK
    Inventors: Hiroyuki Okajima, Kanta Doi
  • Patent number: 10593790
    Abstract: A structure for increasing the concentration of two-dimensional electron gas without lowering mobility is provided. That is, a nitride semiconductor substrate is provided which includes a first layer, a second layer, and a third layer. The first layer has a composition of Ina1Alb1Gac1N (0?a1?1, 0?b1?1, 0?c1?1, a1+b1+c1=1). The second layer is formed on the first layer. The second layer has a composition of Ina2Alb2Gac2N (0?a2?1, 0?b2?1, 0?c2?1, a2+b2+c2=1) and has a band gap different from that of the first layer. The third layer is formed on the second layer and has a composition of AjB1-jN (A is a group 13 element, B is a group 13 element or a group 14 element, A?B, 0<j<1).
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: March 17, 2020
    Assignee: COORSTEK KK
    Inventors: Yoshihisa Abe, Masashi Kobata, Shintaro Miyamoto
  • Patent number: 10559679
    Abstract: There is provided a nitride semiconductor epitaxial substrate having a channel layer, a spacer layer, and an electron supply layer that are stacked in this order. The channel layer is GaN. The spacer layer is AlaGa1-aN (0<a<0.5). The electron supply layer is AlxlnyGa1-x-yN (0<x+y?1). The spacer layer has a thickness of two molecular layers or less.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 11, 2020
    Assignee: COORSTEK KK
    Inventors: Hiroshi Oishi, Noriko Omori, Yoshihisa Abe
  • Publication number: 20190282941
    Abstract: A silicon carbide porous body includes a skeletal structure formed by a plurality of silicon carbide particles bonded to each other, a plurality of pores formed by the skeletal structure, neck parts formed by surface-contacting of adjacent silicon carbide particles, and an average pore size is larger than 3 ?m and equal to or smaller than 9 ?m, and a porosity ranges from 35% to 55%. A break filter using the silicon carbide porous body enables high performance of collection of particles, prevention of soaring up of particles, and shortening of a restoration time from the depressurized state of the chamber to the atmospheric state.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 19, 2019
    Applicant: CoorsTek KK
    Inventors: Seiichi FUKUOKA, Hiroki WATANABE
  • Patent number: 10252933
    Abstract: Provided is a silica glass member which exhibits high optical transparency to vacuum ultraviolet light and has a low thermal expansion coefficient of 4.0×10?7/K or less at near room temperature, particularly a silica glass member which is suitable as a photomask substrate to be used in a double patterning exposure process using an ArF excimer laser (193 nm) as a light source. The silica glass member is used in a photolithography process using a vacuum ultraviolet light source, in which the fluorine concentration is 1 wt % or more and 5 wt % or less, and the thermal expansion coefficient at from 20° C. to 50° C. is 4.0×10?7/K or less.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 9, 2019
    Assignee: COORSTEK KK
    Inventors: Yuji Fukasawa, Sachiko Kato
  • Publication number: 20190074369
    Abstract: There is provided a nitride semiconductor epitaxial substrate having a spacer structure capable of obtaining characteristics unprecedented in the prior art. In the nitride semiconductor epitaxial substrate of the present invention, a channel layer, a spacer layer, and an electron supply layer are stacked in this order. The channel layer is GaN. The spacer layer is AlaGa1?aN (0<a<0.5). The electron supply layer is AlxInyGa1?x?yN (0<x+y?1). The spacer layer has a thickness of two molecular layers or less. Thus, adverse effects due to the existence of a conventional spacer layer are suitably suppressed.
    Type: Application
    Filed: August 17, 2018
    Publication date: March 7, 2019
    Applicant: CoorsTek KK
    Inventors: Hiroshi OISHI, Noriko OMORI, Yoshihisa ABE
  • Patent number: 10222519
    Abstract: A composite silica glass made light diffusion member includes a dense silica glass, and a porous silica glass which has been layered on the surface of the dense silica glass. The porous silica glass is a porous body and has a homogeneous pore distribution. The porous body has a framework including a plurality of spherical silica glasses, contains a communicating pore part formed by spaces among them, and has a central pore size of 10 to 20 ?m and a porosity of 25 to 40%. The spherical silica glasses have an average diameter of 30 to 100 ?m. An average value of a specific arithmetic average roughness Ra in each of the spherical silica glass exposed on an outer surface of the porous silica glass is 0.8 to 4.0 nm.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: March 5, 2019
    Assignee: COORSTEK KK
    Inventors: Yuki Abe, Takeshi Iwasaki, Akira Kanno, Sotaro Takeda, Yutaka Hashimoto
  • Patent number: 10216076
    Abstract: A ceramic composite contains inorganic materials and includes a phosphor phase including YAG containing Ce, and a scatterer phase including a translucent ceramic, in which the phosphor phase is contained in an amount of 90 vol % or more and 99 vol % or less, and the scatterer phase is contained in an amount of 1 vol % or more and 10 vol % or less.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: February 26, 2019
    Assignee: COORSTEK KK
    Inventor: Masaki Irie
  • Patent number: 10170283
    Abstract: There is provided a focus ring formed without an adhesive that can suppress abnormal electric discharge and obtain uniform plasma environment in a circumferential direction in a plasma processing apparatus. The focus ring includes a plurality of arc-shaped members and a plurality of connecting members connecting the plurality of the arc-shaped members to form a ring shape without an adhesive, and is formed such that a thickness between an upper surface of the connecting member and a bottom surface of a concave fitting portion of the connecting member is greater than a thickness between an upper surface of the arc-shaped member and a bottom surface of a second depression of the arc-shaped member.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: January 1, 2019
    Assignee: COORSTEK KK
    Inventors: Masahiro Kubota, Takaaki Shima
  • Publication number: 20180255612
    Abstract: Provided is a planar heater in which a carbon wire heat generator is housed in along quartz glass housing portion, and the planar heater suppresses disconnection of the carbon wire heat generator by limiting a contact region between the carbon wire heat generator and the long housing portion, and capable of efficient radiation heating. In the planar heater, the plurality of long housing portions is disposed on the same plane, and heat is generated by energizing the carbon wire heat generator, each of the plurality of long housing portions is formed in a polygonal circular arc shape in which a plurality of linear portions is connected at a bent portion, respectively, and the plurality of long housing portions is disposed along the circumferences of a plurality of concentric circles.
    Type: Application
    Filed: March 2, 2017
    Publication date: September 6, 2018
    Applicant: CoorsTek KK
    Inventors: Hiroyuki OKAJIMA, Kanta DOI
  • Patent number: 10068858
    Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: September 4, 2018
    Assignee: COORSTEK KK
    Inventors: Yoshihisa Abe, Kenichi Eriguchi, Noriko Omori, Hiroshi Oishi, Jun Komiyama
  • Publication number: 20180240903
    Abstract: A structure for increasing the concentration of two-dimensional electron gas without lowering mobility is provided. That is, a nitride semiconductor substrate is provided which includes a first layer, a second layer, and a third layer. The first layer has a composition of Ina1Alb1Gac1N (0?a1?1, 0?b1?1, 0?c1?1, a1+b1+c1=1). The second layer is formed on the first layer. The second layer has a composition of Ina2Alb2Gac2N (0?a2?1, 0?b2?1, 0?c2?1, a2+b2+c2=1) and has a band gap different from that of the first layer. The third layer is formed on the second layer and has a composition of AjB1-jN (A is a group 13 element, B is a group 13 element or a group 14 element, A?B, 0<j<1).
    Type: Application
    Filed: February 20, 2018
    Publication date: August 23, 2018
    Applicant: CoorsTek KK
    Inventors: Yoshihisa ABE, Masashi KOBATA, Shintaro MIYAMOTO
  • Patent number: 10040693
    Abstract: Particles for a monolithic refractory are made of a spinet porous sintered body which is represented by a chemical formula of MgAl2O4, wherein pores having a pore size of 0.01 ?m or more and less than 0.8 ?m occupy 10 vol % or more and 50 vol % or less with respect to a total volume of pores having a pore size of 10 ?m or less in the particles, and the particles for a monolithic refractory have grain size distribution in which particles having a particle size of less than 45 ?m occupy 60 vol % or less, particles having a particle size of 45 ?m or more and less than 100 ?m occupy 20 vol % or more and 60 vol % or less, and particles having a particle size of 100 ?m or more and 1000 ?m or less occupy 10 vol % or more and 50 vol % or less.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: August 7, 2018
    Assignee: COORSTEK KK
    Inventors: Mitsuhiro Fujita, Shuko Akamine
  • Patent number: 10026633
    Abstract: A wafer boat supporting a silicon wafer to be processed provides a sufficient anchor effect between a deposit film and a SiC coating film formed on a base material, and suppresses generation of particles due to peeling off of the deposit film. The vertical wafer boat includes a plurality of columns, being made of SiC-based material having a SiC coating film on a surface thereof, which contains shelf plate portions for supporting wafers, and a top plate and a bottom plate for fixing upper and lower ends of the columns, wherein a supporting plane which is in contact with an outer peripheral portion of the wafer is provided on an upper surface of the shelf plate portion, and a surface roughness Ra of a lower surface of the shelf plate increases toward a front side of the shelf plate portion from a rear side.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: July 17, 2018
    Assignee: COORSTEK KK
    Inventor: Takeshi Ogitsu
  • Patent number: 10008402
    Abstract: A vertical wafer boat includes a top plate, a bottom plate, three support posts, and wafer support parts. The support posts include a first and a second support posts arranged in right and left sides of a starting end side of a wafer inserting direction, and a third support post arranged in a center of a terminal end side of the wafer inserting direction. The wafer support parts include a first, second and third wafer support parts protruding in the horizontal direction from side surfaces of the first, second and third support posts, respectively. A total of horizontal sectional areas of the first wafer support part and the first support post, or the second wafer support part and the second support post, and a total of horizontal sectional areas of the third wafer support part and the third support post have a specific relationship.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 26, 2018
    Assignee: COORSTEK KK
    Inventor: Takeshi Ogitsu
  • Publication number: 20180151714
    Abstract: Provided is a nitride semiconductor substrate which improves electron mobility and reduce a series resistance component of a transistor. In the nitride semiconductor substrate, an electron transit layer, an intermediate layer, and an electron supply layer are laminated in this order. The electron transit layer includes a nitride semiconductor of a first group 13 element. The intermediate layer and the electron supply layer each include a nitride semiconductor of the first group 13 element and a second group 13 element. The nitride semiconductor substrate has a profile in which an atomic ratio of the second group 13 element to a total of the first group 13 element and the second group 13 element increases in the thickness direction of the intermediate layer from an interface between the electron transit layer and the intermediate layer, and the atomic ratio decreases after a maximum peak value is obtained in the intermediate layer.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 31, 2018
    Applicant: CoorsTek KK
    Inventors: Noriko OMORI, Hiroshi OISHI, Yoshihisa ABE, Jun KOMIYAMA
  • Patent number: 9938195
    Abstract: A heat insulating material includes a porous sintered body formed of MgAl2O4 and having a porosity of 60% or more and less than 73%. In the heat insulating material, pores having a pore diameter of 0.8 ?m or more and less than 10 ?m occupy 30 vol % or more and less than 90 vol % of a total pore volume, pores having a pore diameter of 0.01 ?m or more and less than 0.8 ?m occupy 10 vol % or more and less than 60 vol % of the total pore volume, the thermal conductivity at 20° C. or higher and 1500° C. or lower is 0.45 W/(m·K) or less, and the compressive strength is 2 MPa or more.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: April 10, 2018
    Assignee: COORSTEK KK
    Inventors: Shuko Akamine, Mitsuhiro Fujita
  • Publication number: 20180019144
    Abstract: A vertical wafer boat includes a plurality of struts formed with a shelf plate portion configured to mount a silicon wafer, and a top plate and a bottom plate which fix upper and lower ends of the struts. The shelf plate portion is inclined downward toward the center of the boat, and a wafer support portion which protrudes upward and abuts on an edge portion of the silicon wafer is formed at a distal end of the shelf plate portion. To obtain the vertical wafer boat which supports a silicon wafer to be processed by a shelf plate portion provided in multiple stages, the vertical wafer boat being capable of reducing a risk of contact between a warped outer peripheral portion of a wafer and the shelf plate portion and suppressing deflection of the silicon wafer even when the silicon wafer has a large diameter.
    Type: Application
    Filed: July 10, 2017
    Publication date: January 18, 2018
    Applicant: CoorsTek KK
    Inventor: Takeshi OGITSU
  • Patent number: 9868270
    Abstract: Provided is a wavelength converting member made of a sintered body which inhibits color unevenness of exit light after wavelength conversion and has excellent light emitting efficiency and inhibited decrease in mechanical strength. The wavelength converting member includes a plate-like sintered body having one principal surface as a light entrance surface and the other principal surface as a light exit surface, and a porosity of 0.1% or less with fluorescent material grains containing an activator and light-transmitting material grains, the entrance surface and the exit surface are sintered surfaces in which the fluorescent material grains and light-transmitting material grains are exposed without processing. The sintered surface has an average roughness Ra of 0.1 ?m to 0.5 ?m, the fluorescent material grains exposed on a surface have an average roughness Ra1 of 0.2 nm to 0.5 nm, and the light-transmitting material grains exposed on a surface have an average roughness Ra2 of 0.3 nm to 0.7 nm.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: January 16, 2018
    Assignee: COORSTEK KK
    Inventor: Masaki Irie
  • Publication number: 20170349477
    Abstract: Provided is a silica glass member which exhibits high optical transparency to vacuum ultraviolet light and has a low thermal expansion coefficient of 4.0?10?7/K or less at near room temperature, particularly a silica glass member which is suitable as a photomask substrate to be used in a double patterning exposure process using an ArF excimer laser (193 nm) as a light source. The silica glass member is used in a photolithography process using a vacuum ultraviolet light source, in which the fluorine concentration is 1 wt % or more and 5 wt % or less, and the thermal expansion coefficient at from 20° C. to 50° C. is 4.0×10?7/K or less.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 7, 2017
    Applicant: CoorsTek KK
    Inventors: Yuji FUKASAWA, Sachiko KATO