Patents Assigned to CoorsTek KK
  • Patent number: 9784403
    Abstract: One aspect of the heat insulator of the present invention includes a porous sintered body having a porosity of 70 vol % or more and less than 91 vol %, and pores having a pore size of 0.8 ?m or more and less than 10 ?m occupy 10 vol % or more and 70 vol % or less of the total pore volume, while pores having a pore size of 0.01 ?m or more and less than 0.8 ?m occupy 5 vol % or more and 30 vol % or less of the total pore volume. The porous sintered body is formed from an MgAl2O4 (spinel) raw material and fibers formed of an inorganic material, the heat conductivity of the heat insulator at 1000° C. or more and 1500° C. or less is 0.40 W/(m·K) or less, and the weight ratio of Si relative to Mg in the porous sintered body is 0.15 or less.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 10, 2017
    Assignee: COORSTEK KK
    Inventors: Shuko Akamine, Mitsuhiro Fujita
  • Patent number: 9748344
    Abstract: The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 3×108 pieces/cm2 or more and 1×1011 pieces/cm2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: August 29, 2017
    Assignee: COORSTEK KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi, Tomoko Watanabe
  • Publication number: 20170217781
    Abstract: Particles for a monolithic refractory are made of a spinet porous sintered body which is represented by a chemical formula of MgAl2O4, wherein pores having a pore size of 0.01 ?m or more and less than 0.8 ?m occupy 10 vol % or more and 50 vol % or less with respect to a total volume of pores having a pore size of 10 ?m or less in the particles, and the particles for a monolithic refractory have grain size distribution in which particles having a particle size of less than 45 ?m occupy 60 vol % or less, particles having a particle size of 45 ?m or more and less than 100 ?m occupy 20 vol % or more and 60 vol % or less, and particles having a particle size of 100 ?m or more and 1000 ?m or less occupy 10 vol % or more and 50 vol % or less.
    Type: Application
    Filed: December 20, 2016
    Publication date: August 3, 2017
    Applicant: CoorsTek KK
    Inventors: Mitsuhiro FUJITA, Shuko AKAMINE
  • Publication number: 20170110414
    Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.
    Type: Application
    Filed: October 4, 2016
    Publication date: April 20, 2017
    Applicant: COORSTEK KK
    Inventors: Yoshihisa ABE, Kenichi ERIGUCHI, Noriko OMORI, Hiroshi OISHI, Jun KOMIYAMA
  • Publication number: 20170011919
    Abstract: The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 3×108 pieces/cm2 or more and 1×1011 pieces/cm2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.
    Type: Application
    Filed: July 6, 2016
    Publication date: January 12, 2017
    Applicant: CoorsTek KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi, Tomoko Watanabe
  • Patent number: 9536955
    Abstract: A nitride semiconductor substrate is provided which is suitable for a high withstand voltage power device and prevents a warp and a crack from generating in a Si substrate when forming a thick nitride semiconductor layer on the substrate. A nitride semiconductor substrate 1 is prepared in such a manner that a buffer layer 3 and a semiconductor active layer 4 each comprising a group 13 nitride are stacked one by one on one principal plane of a Si single crystal substrate, the one principal plane has an offset angle of 0.1° to 1° or ?1° to ?0.1° with respect to a (111) plane, an average dopant concentration in a bulk is 1×1018 to 1×1021 cm?3, the Si single crystal substrate 2 has a SiO2 film on the back, and the total thickness of the buffer layer 3 and the semiconductor active layer 4 is 4 to 10 ?m.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 3, 2017
    Assignee: COORSTEK KK
    Inventors: Jun Komiyama, Kenichi Eriguchi, Akira Yoshida, Hiroshi Oishi, Yoshihisa Abe, Shunichi Suzuki
  • Publication number: 20160379859
    Abstract: A wafer boat supporting a silicon wafer to be processed provides a sufficient anchor effect between a deposit film and a SiC coating film formed on a base material, and suppresses generation of particles due to peeling off of the deposit film. The vertical wafer boat includes a plurality of columns, being made of SiC-based material having a SiC coating film on a surface thereof, which contains shelf plate portions for supporting wafers, and a top plate and a bottom plate for fixing upper and lower ends of the columns, wherein a supporting plane which is in contact with an outer peripheral portion of the wafer is provided on an upper surface of the shelf plate portion, and a surface roughness Ra of a lower surface of the shelf plate increases toward a front side of the shelf plate portion from a rear side.
    Type: Application
    Filed: June 15, 2016
    Publication date: December 29, 2016
    Applicant: CoorsTek KK
    Inventor: Takeshi OGITSU
  • Patent number: 9530846
    Abstract: A solution is formation of a nitride semiconductor layer on one principal plane of a single crystal substrate through a first layer. Upon selecting arbitrary three places in a radial direction from a cross section cleaved in a diameter portion and observing an interface between the first layer and the nitride semiconductor layer by taking a width of at least 500 nm in the radial direction, a value is within the range of 6 nm or more and 15 nm or less in a mean value of the three places with regard to a difference between a maximum height of a convex top portion and a minimum height of a concave bottom portion of the first layer in a thickness direction from the single crystal substrate toward the nitride semiconductor layer. A value is 10 nm or more and 25 nm or less in the mean value.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 27, 2016
    Assignee: CoorsTek KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi
  • Publication number: 20160293710
    Abstract: A solution is formation of a nitride semiconductor layer on one principal plane of a single crystal substrate through a first layer. Upon selecting arbitrary three places in a radial direction from a cross section cleaved in a diameter portion and observing an interface between the first layer and the nitride semiconductor layer by taking a width of at least 500 nm in the radial direction, a value is within the range of 6 nm or more and 15 nm or less in a mean value of the three places with regard to a difference between a maximum height of a convex top portion and a minimum height of a concave bottom portion of the first layer in a thickness direction from the single crystal substrate toward the nitride semiconductor layer. A value is 10 nm or more and 25 nm or less in the mean value.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 6, 2016
    Applicant: CoorsTek KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi
  • Patent number: 9428728
    Abstract: A colony (cell mass) proliferated under the undifferentiated state is obtained by using a carrier for cell culture in which two or more of a concavity having a porous body in a surface are arranged on a substrate surface in the form of a matrix, inoculating an undifferentiated cell on at least one concavity of the carrier for culture and carrying out culture.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: August 30, 2016
    Assignee: COORSTEK KK
    Inventors: Fumihiko Kitagawa, Takafumi Imaizumi, Katsunori Sasaki
  • Publication number: 20160233117
    Abstract: Provided is a vertical wafer boat with columns having a rectangular cross section, and capable of making a flow of a film-forming gas between wafer support portions more uniform, suppressing variation in the film thickness in a wafer plane, and forming a more uniform film. A vertical wafer boat includes columns on which wafer support portions for mounting a plurality of wafers are formed, and a top plate and a bottom plate that fix upper and lower end portions of the columns. At least one of the columns includes two column portions and extending in an up and down direction and having a rectangular cross section, and a plurality of the wafer support portions that connects the two column portions and mounts wafers on upper surfaces.
    Type: Application
    Filed: February 10, 2016
    Publication date: August 11, 2016
    Applicant: CoorsTek KK
    Inventors: Shigeaki KUROI, Tomokazu KIMURA, Jianhui LI