Abstract: A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the “add-in” values, and another vector register is loaded with address values of “add to” elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the “add in” values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the “gather” operation to load the “add to” values. A vector add operation then adds corresponding elements from the “add in” vector to the “add to” vector. An indirectly addressed store then performs the “scatter” operation to store the results.

Abstract: Cooling systems for use with computer systems are disclosed herein. In one embodiment, a computer system includes a first computer module spaced apart from a second computer module to define a space therebetween. The computer system further includes a cooling system positioned in the space between the first and second computer modules. The cooling system includes a first heat exchanging portion containing a working fluid that absorbs heat from an electronic device mounted to the first computer module. The cooling system further includes a second heat exchanging portion that receives the heated working fluid from the first heat exchanging portion to cool the heated working fluid. A fluid mover is operably coupled to the first and second heat exchanging portions to circulate the working fluid through the first and second heat exchanging portions.

Abstract: A method and apparatus for a coherence mechanism that supports a distributed memory programming model in which processors each maintain their own memory area, and communicate data between them. A hierarchical programming model is supported, which uses distributed memory semantics on top of shared memory nodes. Coherence is maintained globally, but caching is restricted to a local region of the machine (a “node” or “caching domain”). A directory cache is held in an on-chip cache and is multi-banked, allowing very high transaction throughput. Directory associativity allows the directory cache to map contents of all caches concurrently. References off node are converted to non-allocating references, allowing the same access mechanism (a regular load or store) to be used for both for intra-node and extra-node references. Stores (Puts) to remote caches automatically update the caches instead of invalidating the caches, allowing producer/consumer data sharing to occur through cache instead of through main memory.

Abstract: A system and method for routing packets from one node to another node in a system having a plurality of nodes connected by a network. A node router is provided in each node, wherein the node router includes a plurality of network ports, including a first and a second network port, wherein each network port includes a communications channel for communicating with one of the other network nodes, a plurality of virtual channel input buffers and a plurality of virtual channel staging buffers, wherein each of the virtual channel staging buffers receives data from one of the plurality of input buffers.

Abstract: A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.

Abstract: A system and method for routing a packet between ports for use in a router having a plurality of ports, including a first and a second port, wherein each port includes a plurality of look-up tables (LUTs) and a look-up table select connected to the LUTs. Routing information is loaded into each of the plurality of LUTs while LUT selection information is loaded in the look-up table select. A packet having a plurality of destination bits is received at the first port and a destination port selected within the router to receive the packet. The destination port is selected by applying two or more of the destination bits to the plurality of LUTs in the first port and selecting an output of the plurality of LUTs as a function of one or more of the destination bits, wherein the selected output indicates the port selected to receive the packet. The packet is then routed to the output of the selected port.

Abstract: A system and method of building a routing table for use in a multiprocessor computer system having a plurality of processing nodes and physical communication links interconnecting the processing nodes in a predefined topology. The system determines all single hops for each processing node, queries each adjacent node for its single hop routes, determines if all nodes can be reached and if all nodes cannot be reached, sets x=2. The system then queries each adjacent node for its “x” hop routes, eliminates all routes to a particular node that are longer than existing routes from the node where the routing table will reside to that particular node, eliminates all routes that introduce a cyclic dependency and chooses a best route for the node. The process is repeated as needed until all nodes can be reach all other nodes.

Abstract: A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the “add-in” values, and another vector register is loaded with address values of “add to” elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the “add in” values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the “gather” operation to load the “add to” values. A vector add operation then adds corresponding elements from the “add in” vector to the “add to” vector. An indirectly addressed store then performs the “scatter” operation to store the results.

Abstract: Flow conditioners for use with air inlets on computer cabinets are disclosed herein. In one embodiment, a large computer system includes a plurality of computer cabinets arranged in close proximity to each other. Each of the computer cabinets can include a fan, impellor, or other air mover positioned proximate to an inlet that receives cooling air from a plenum, such as a floor plenum. In this embodiment, a flow conditioner configured in accordance with the present invention can be positioned proximate to the air inlet. The flow conditioner can include a vortex diffuser and a flow-speed normalizer. The flow-speed normalizer can include a perforated screen that forms a cylinder around the inlet, and the vortex diffuser can include one or more vanes that extend across the cylinder adjacent to the inlet.

Abstract: A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: In a computer system having a scalar processing unit and a vector processing unit, wherein the vector processing unit includes a vector dispatch unit, a system and method of decoupling operation of the scalar processing unit from that of the vector processing unit, the method comprising sending a vector instruction from the scalar processing unit to the vector dispatch unit, wherein sending includes marking the vector instruction as complete if the vector instruction is not a vector memory instruction and if the vector instruction does not require scalar operands, reading a scalar operand, wherein reading includes transferring the scalar operand from the scalar processing unit to the vector dispatch unit, predispatching the vector instruction within the vector dispatch unit if the vector instruction is scalar committed, dispatching the predispatched vector instruction if all required operands are ready, and executing the dispatched vector instruction as a function of the scalar operand.

Abstract: Systems and methods for cooling computer components in large computer systems are disclosed herein. In one embodiment, a computer system configured in accordance with aspects of the invention can include a computer module positioned in a chassis, and an air mover configured to move air through the chassis and past the computer module. The computer system can further include a pressure sensor operably coupled to the air mover. If the pressure sensor determines that the difference between a first air pressure inside the chassis and a second air pressure outside the chassis is less than a preselected pressure, the air mover can increase the flow of air through the chassis and past the computer module.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: Systems and methods for absorbing acoustic noise generated by computer cabinet cooling fans are described herein. In one embodiment, an acoustic absorber for use with a fan carried by a computer cabinet in a room includes a first acoustic panel spaced apart from a second acoustic panel. The first acoustic panel is configured to be positioned proximate to an outlet of the fan and at least approximately parallel to a flow of cooling air discharging from the outlet. The second acoustic panel is also configured to be positioned proximate to the outlet of the fan and at least approximately parallel to the flow of cooling air discharging from the outlet. The first and second acoustic panels together form an opening configured to direct the flow of cooling air away from the fan outlet and into the surrounding room. In a further embodiment, the opening formed by the first and second acoustic panels can be configured to extend at least approximately 360 degrees around the fan.

Abstract: Cooling systems for use with computer systems are disclosed herein. In one embodiment, a computer system includes a first computer module spaced apart from a second computer module to define a space therebetween. The computer system further includes a cooling system positioned in the space between the first and second computer modules. The cooling system includes a first heat exchanging portion containing a working fluid that absorbs heat from an electronic device mounted to the first computer module. The cooling system further includes a second heat exchanging portion that receives the heated working fluid from the first heat exchanging portion to cool the heated working fluid. A fluid mover is operably coupled to the first and second heat exchanging portions to circulate the working fluid through the first and second heat exchanging portions.

Abstract: Apparatuses and methods for cooling processors and other electronic components in computers and other systems are disclosed herein. A heat sink configured in accordance with one embodiment of the invention includes a heat pipe structure. The heat pipe structure includes an interface portion offset from a body portion by a leg portion. The interface portion is configured to be positioned proximate to a processor or other electronic device, and the body portion is configured to be spaced apart from the electronic device. The heat pipe structure further includes a working fluid. The working fluid is positioned to absorb heat from the electronic device at the interface portion of the heat pipe structure and transfer the heat to the body portion of the heat pipe structure. In one embodiment, the heat sink can further include a plurality of cooling fins attached to the body portion of the heat pipe structure.

Abstract: A memory module comprises a plurality of storage bits for each memory location, and a plurality of error management storage bits for each memory location. A memory controller is operable to change error management modes on the memory module. Changing error management modes comprises in one example using an error management mode providing the greatest error management capability for the number of operable memory components available within the memory module.

Abstract: A method and system for selectively enabling a cache-invalidate function supplement to a resource-synchronization instruction such as test-and-set. Some embodiments include a first processor, a first memory, at least a first cache between the first processor and the first memory, wherein the first cache caches data accessed by the first processor from the first memory, wherein the first processor executes: a resource-synchronization instruction, an instruction that enables a cache-invalidate function to be performed upon execution of the resource-synchronization instruction, and an instruction that disables the cache-invalidate function from being performed upon execution of the resource-synchronization instruction.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.