Abstract: Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit operable to detect a multi-bit error in data read from the memory device, and to retry the read operation in order to distinguish between an intermittent error and a persistent error.

Abstract: A spray cooling system includes a spray delivery device and a cooling liquid delivered to the spray delivery device. The spray delivery device includes one or more inlet apertures and one or more corresponding outlet apertures, at least one pair of inlet aperture and corresponding outlet aperture being positioned relative to each so as to form an asymmetric non-uniform density full-cone spray pattern.

Abstract: An apparatus comprising a first multiplexer circuit (MUX) to receive a plurality of clock phase signals at a corresponding plurality of MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a phase delay circuit to receive the output of the first MUX and to generate adjusted first and second clock signals that have reduced phase error with respect to detected edges of incoming data, an output MUX to receive the adjusted first and second clock signals and to output a recovered clock signal, and a control circuit coupled to output MUX select inputs. The control circuit includes logic circuitry to select the first adjusted clock signal as the recovered clock signal and to select the second adjusted clock signal as the recovered clock signal when the first adjusted clock signal nears a phase limit due to drift of the detected data edges. Other devices and methods are disclosed.

Abstract: In a computer system having a plurality of processors connected to a shared memory, a system and method of decoupling an address from write data in a store to the shared memory. A write request address is generated for a memory write, wherein the write request address points to a memory location in shared memory. A write request is issued to the shared memory, wherein the write request includes the write request address. The write request address is noted in the shared memory and addresses in subsequent load and store requests are compared in share memory to the write request address. The write data is transferred to the shared memory and matched, within the shared memory, to the write request address. The write data is then stored into the shared memory as a function of the write request address.

Abstract: A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace information, target source code of interest is compiled in such a manner that executing the resulting executable code will generate execution trace information composed of a series of events. Each event stores trace information related to a variety of performance measures for the one or more processors and protection domains used. After the execution trace information has been generated, the system can use that trace information and a trace information description file to produce useful performance measure information. The trace information description file contains information that describes the types of execution events as well as the structure of the stored information.

Abstract: Systems and methods start a process in an operating system. Additionally, a plurality of program units associated with the process are started. When a context shifting event occurs, each of the plurality of program units has their scheduling synchronized and their context set so that each thread processes the context shifting event. A further aspect of the system is that some program units may be executing on more than one multiple processor unit. In the operating system selects a multiple processor unit to host all of the program units, and migrates those program units that are not currently on the selected multiple processor unit to the selected multiple processor unit.

Abstract: A multiprocessor computer system batch system interface between an application level placement scheduler and one or more batch systems comprises a predefined protocol operable to convey processing node resource request and availability data between the application level placement scheduler and the one or more batch systems.

Abstract: A multiprocessor computer system reservation system comprises a plurality of processing nodes that each comprise computing resources such as processors and local memory. A resource reservation module is operable to reserve computing resources for a batch application such that the computing resources reserved for the batch application will be available to the application throughout a reservation period. The resource reservation module is operable to communicate computing resource reservation information with a placement scheduler that is operable to distribute application processes across processing nodes, and is operable to provide computing resource availability information to a batch system and to place reservations for a batch system that comprises a mechanism for scheduling batch jobs across processing nodes.

Abstract: A multiprocessor computer system program scheduler comprises an application-level placement scheduler module that is operable to receive requests for resources in a multiprocessor computer system, operable to manage processing node resource availability data; operable to reserve processing node resources for specific applications based on the received requests for resources and the processing node resource availability data; and operable to reclaim processing node resources reserved for specific applications upon application termination.

Abstract: A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.

Abstract: A multiprocessor computer system having a plurality of processing elements comprises one or more core-level hierarchical shared semaphore registers, wherein each core-level hierarchical shared semaphore register is coupled to a different processor core. Each hierarchical shared semaphore register is writable to each of a plurality of streams executing on the coupled processor core. One or more chip-level hierarchical shared semaphore registers are also coupled to plurality of processor cores, each chip-level hierarchical shared semaphore register writable to each of the plurality of processor cores.

Abstract: A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space.

Abstract: Embodiments include a system and method for generating RTL description of an electronic device provided for a design test and a test bench environment to drive stimulus into the electronic device, identifying at least one register to be verified during the design test, authoring a property list including a plurality of properties, wherein each property includes a cause and an effect, creating a new property instance upon receiving an enqueue cause, transitioning a property instance from a waiting state to a pending state based on a dequeue cause, advancing property instances from the pending state to an active state and then to an expired state based on a defined time window, creating a current solution space including a plurality of solutions, wherein each of the plurality of solutions includes a list of unused active effects, inserting property instances into each of the plurality of solutions when the property instance enters to active state, pruning solutions from the current solutions space which have no

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: This document describes, among other things, a computerized system comprising a plurality of processing nodes, a physical channel configured to transfer data between a memory local to a processing node and a network target remote from the processing node, and a block transfer engine configured to allocate a plurality of virtual channels to the physical channel and to transfer a plurality of address-overlapping blocks of data simultaneously using the virtual channels.

Abstract: Multi-stage air movers for cooling computers and other systems are described herein. In one embodiment, a computer system includes a computer cabinet holding a plurality of computer modules. The computer cabinet includes an air inlet and an air outlet. The computer system further includes a multi-stage air mover configured to move a flow of cooling air from the air inlet, past the plurality of computer modules, and out the computer cabinet via the air outlet.

Abstract: Control messages are sent from a control processor to a plurality of attached processors via a control tree structure comprising the plurality of attached processors and branching from the control processor, such that two or more of the plurality of attached processor nodes are operable to send messages to other attached processor nodes in parallel.

Abstract: A method and system for allocating and de-allocating memory for threads of an application is provided. An allocation system provides a heap for tracking free tokens of memory that are available for allocation to threads of an application. A heap tracks collections of free tokens of the fixed token size. The allocation system receives memory requests from threads that specify an allocation type of allocate or de-allocate. When multiple memory requests are pending concurrently from multiple threads, then the allocation system attempts to combine memory requests of the same type and of the same token size that are received from different threads. One of the threads is responsible for updating the heap to effect the two memory requests. The allocation system combines multiple memory requests so that the heap need only be accessed once to allocate or de-allocate multiple tokens.

Abstract: One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode including a second anode and a second cathode, with the second cathode coupled to the node via a second mechanical switch, the second anode coupled to a ground and a resistor coupled to the input circuit between the integrated circuit and the node, wherein in a first mode of operating, the first mechanical switch and the second mechanical switch are conducting, and in a second mode of operating, the first and second mechanical switches are nonconducting.

Abstract: An apparatus comprising a transmission line, a receiver circuit, and a high pass filter circuit coupled between the transmission line and a receiver circuit input. The receiver circuit is configured to receive a data signal over the transmission line at a first data rate. The high pass filter circuit is connected between the transmission line and a receiver circuit input and has a corner frequency that is less than approximately the first data rate and is greater or equal to than approximately one-half the second data rate. The second data rate is an effective data rate caused by an expected data pattern on the transmission line. Other devices, systems, and methods are disclosed.