Abstract: An integrated circuit (IC) tester includes several processing nodes, each accessing a separate terminal of an IC to be tested. The tester receives as input a description of an integrated circuit test to be conducted. The description indicates actions to be taken at each processing node and a time relative to the start of the test that each action is to be taken. The actions may include transmitting a test signal to the IC or sampling an output signal produced by the IC. Before starting the test, the tester converts the description into a set of algorithms for generating test vectors and stores each algorithm in a separate processing node. The test is organized into a succession of test cycles and during the test, each node executes its stored algorithm, generating a separate test vector at the beginning of each test cycle. The test vector indicates an action to be taken by that node during the following test cycle along with a time during the test cycle that the action is to be taken.

Abstract: An apparatus for performing logic and leakage current tests on a logic circuit device under test (DUT) includes a local module for each terminal of the DUT. For performing logic test, each local module has a driver for supplying a logic signal input to the DUT terminal, a comparator for detecting the DUT output at the terminal, and a clamping circuit for limiting the voltage swing at the DUT terminal during the logic test. For performing a leakage current test, each local module includes a source for supplying a parametric signal to the DUT terminal. The voltage the parametric signal produces at the DUT terminal, as detected by the comparator, indicates the terminal's leakage current. The parametric signal source and the clamping circuit are connected to the DUT terminal through Schottky diodes. During a logic test the parametric signal source is isolated from the DUT terminal by reverse biasing the Schottky diodes linking the parametric signal source to the DUT terminal.

Abstract: A timing signal generator includes a voltage controlled oscillator (VCO), a logic circuit, N set circuits and N reset circuits and a bistable latch circuit. The VCO produces a set of N reference signals frequency locked to a reference clock signal and distributed in phase so as to evenly resolve the reference clock period into N intervals. The logic circuit asserts ones of N set signals and N reset signals selected by input control words. Each set circuit receives one of the N set signals and one of the N reference signals and briefly couples an output node to high logic level source in response to a leading edge of the received reference signal when its received set signal is asserted. Each reset circuit receives one of the N reset signals and one of the N reference signals and briefly couples the output node to low logic level source in response to a leading edge of its received reference signal when it reset signal is asserted.

Abstract: A timing vernier produces a set of timing signals of similar frequency and evenly distributed in phase by passing an input reference clock signal through a succession of delay stages, each stage providing a similar signal delay. A separate one of the timing signals is produced at the output of each delay stage. The reference clock signal and timing signal output of the last delay stage are supplied as inputs to a phase lock controller through separate adjustable first and second delay circuits. The phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. In accordance with the invention, the delays of the first and second delay circuits are adjusted to compensate for controller phase lock error.

Abstract: Apparatus for testing an integrated circuit device (DUT) having an input port and an output port comprises multiple state devices each having multiple states that occur in a predetermined sequence and each having an output port at which it provides an event signal representative of its current state. At least a first of the state devices is an emitting device that emits an event marker signal at a predetermined time in advance of entering a predefined state, at least a second of the state devices is a receiving device that responds to receipt of an event marker signal in a predetermined manner after lapse of a predetermined time, at least one of the state devices has its output port connected to the input port of the DUT, and at least one of the state devices is a measurement device connected to the output port of the DUT. An interconnection matrix is connected to each state device and allows each state device to communicate an event marker signal to each other state device.

Abstract: A timing signal generator produces a timing signal having one or more pulses of adjustable phase relative to pulses of a stable reference clock. The timing signal generator employs a low jitter retriggerable oscillator to produce a set of tap signals. The tap signals are frequency locked to the reference clock signal but are evenly distributed in phase. The timing signal generator times the pulses of its output timing signal using pulses of the various tap signals as timing references. Each cycle of the oscillator is triggered by a pulse of the reference clock signal to minimize timing signal jitter. Phase lock loops frequency lock the tap signals to the reference clock and ensure predictability of the timing signal pulse timing relative to the reference clock signal.

Abstract: A system manipulates stimulus/response signal data associated with an integrated circuit design, such as from a computer-aided engineering simulator, and converts the data into a format acceptable by a tester device which tests a prototype or production integrated circuit. The data is graphically displayed as a waveform and as a vector sequence. On-screen editing of either display is reflected in the other display. Further, the same displays are used to convert the data from event-based data into cycle-based template data compatible with a tester. A mix between event and state data during the conversion is allowed. A standard frame generation language is presented for defining tester frames for each signal within a template or timeset. A workbench editor provides for icon-based control of the system.

Abstract: An embodiment of the present invention is a retriggered oscillator timebase including a phase lock loop controlled ring for direct retriggering by a reference oscillator. The ring has taps at various successive stages that are output to an on-the-fly selector that can add any ten-bit value to a current-tap selection to enable a next-tap selection. Such on-the-fly addition can increase the period of a signal each cycle and thereby divide the reference frequency. Ring outputs are also used to drive two other retriggered rings for a plurality of NANO timing generators. The use of two rings allows retriggering of one of the rings before the other has completed a whole one-shot cycle. An on-the-fly selector subtracts a value from a present "NANO" select to a next "NANO" select to convert back the timebase to the fixed reference frequency for phase and frequency comparison. The subtraction acts as a frequency multiplication whose output "t.sub.0fx " is equal to the reference frequency.

Abstract: A dual-function DUT board connection and disconnection and prober/handler docking system is easy to use and provides high quality parallel electrical interconnection for a large number of signals by exerting a proper amount of pressure over a large but variable connection area with a high degree of reliability. A cam-ring is rotatably mounted to a load board. A DUT board, a DUT board holddown ring with cam followers and (optional) layers of pin-protecting plastic rings are aligned by two alignment pins on the load board into a correct position for mating of electrical connections between the load board and the DUT board. Rotation of the cam-ring by attached handles forces cam followers on the DUT board holddown ring to be drawn closer to the load board, bringing the DUT board into suitable electrical contact with connectors that electrically connect the DUT board to the load board.