Abstract: An integrated circuit tester includes a host computer, a pattern generator and a set of tester circuits for performing a series of tests on an integrated circuit. The pattern generator is programmed to supply a sequence of pattern data as input to the tester circuits for controlling their operations during each test of the series. The pattern generator may also be programmed to interrupt the host computer before or during any test whenever it is necessary for the host computer to carry out an activity. The host computer may be programmed to respond to an interrupt by writing parameter control data into the tester circuits to reconfigure their operating characteristics, by acquiring test results from the tester circuits, or by directly controlling tester circuit operations during a test. When necessary to provide sufficient time for the host computer to carry out its task, the pattern generator may be programmed to temporarily suspend supplying pattern data to the tester circuits after sending an interrupt.

Abstract: In an integrated circuit tester module, pin electronics circuitry supplies leakage current to a circuit node which is connected to a signal pin of a device under test. The leakage current is compensated by connecting the circuit node to a voltage source at a first potential level, supplying current to the circuit node from a second potential level, and measuring current supplied to the circuit node from the voltage source. The second potential level is selectively varied in a manner such as to reduce the current supplied from the voltage source substantially to zero. The circuit node is then disconnected from the voltage source.

Abstract: A probe assembly contacts pins of a flat pack or other integrated circuit (IC) package having a body with a flat upper surface and a plurality of pins extending horizontally outward from the IC package body. The probe assembly includes a base that is bonded to the upper surface of the IC package body by a thermal-releasing adhesive when the base is pressed onto the IC package body. A set of probes (spring pins) extending downward from the base contact the IC pins when the base is bonded to the IC package body. The base includes a heating element for supplying heat to warm the adhesive and weaken the adhesive bond when the probe assembly is to be removed from the IC package. The heating element generates the heat in response to a current pulse passing through the heating element or alternatively receives the heat from an external source and conducts it to the adhesive.

Abstract: A test head for a semiconductor integrated circuit tester comprises a housing which has an air inlet opening and an air outlet opening and bounds a pin card space and an air chamber. Multiple pin cards are located in the pin card space and radiate from an interior cavity which is within the pin card space. A baffle structure divides the air chamber, which is separated from the pin card space by a boundary surface, into an air supply duct which provides communication between the air inlet opening and the interior cavity and an outlet plenum which provides communication between the pin card space and the air outlet opening by way of the boundary surface. A fan is mounted in the interior cavity for inducing a flow of air from the interior cavity to the plenum by way of spaces between the pin cards.

Abstract: An integrated circuit (IC) tester includes set of tester channels, each for carrying out a test activity at a separate terminal of an IC device under test (DUT) during each cycle of a test. The tester also includes a disk drive having a removable disk for reading out scan or programming data to the tester channels during a test. Each tester channel includes an instruction memory for storing a set of instructions, and each tester channel executes its stored instructions during the test. Some of the instructions include VECTOR data directly indicating a particular test activity the tester channel is to carry out at a DUT terminal during a next test cycle. Others of the instructions tell the tester channel to acquire a particular number (N) of serial data bits as they are read out of the disk drive and to carry out an activity during each of the next N test cycles indicated by a state of a corresponding one of the N serial data bits.

Abstract: An integrated circuit (IC) tester includes a set of dual-purpose digital/analog channels. Each tester channel includes a driver capable of supplying either a digital or analog test signal input to an IC terminal and a receiver for digitizing and processing either an analog or digital IC output signal appearing at the DUT terminal to produce results data representing the behavior of that IC output signal during a test. A test is organized into a succession of test cycles, and before each test cycle a pattern generator within each channel produces data for controlling the behavior of the driver and receiver during the test cycle. The control data controls whether the driver is to produce an analog or a digital test signal, controls a magnitude or logic level to which the test signal is to be driven during the test cycle, and controls a time during the test cycle of any test signal state or magnitude changes.

Abstract: A test pattern generator for a semiconductor integrated circuit tester comprises a DRAM for receiving and storing test pattern data in blocks and a SRAM for storing checking data in units, wherein each unit of checking data stored in the SRAM bears a predetermined relationship to a corresponding block received by the DRAM. A DRAM sequencer addresses the DRAM for reading the blocks of test pattern data in a predetermined order and a SRAM sequencer addresses the SRAM for reading the units of checking data from the SRAM. A validating circuit receives a block of test pattern data read from the DRAM and the corresponding unit of checking data read from the SRAM and provides an output which indicates whether the unit of checking data is in the predetermined relationship with the block.

Abstract: A system for stabilizing a delay through a signal path of an integrated circuit (IC) includes an oscillator for producing a periodic first reference signal, a delay circuit for delaying the first reference signal to produce a periodic second reference signal, and a loop controller for adjusting the magnitude of the IC's power supply so as to maintain a constant phase difference between the first and second reference signals. By adjusting the power supply magnitude, the loop controller also stabilizes signal path delays through logic circuits implemented in the IC. The oscillator is formed by a logic gate implemented in the IC and a passive delay line feeding the logic gate's output back to its input. The delay of the delay circuit is programmably adjustable to allow for adjustment of the signal path delay through the IC.

Abstract: An integrated circuit (IC) tester includes a set of digital and analog channels, each of which may be programmed to carry out a sequence of test activities at pins of an IC under test. The channels are interconnected by a trigger bus, and each channel may be programmed to respond to a detected event during a test by transmitting a particular trigger code to every other channel via the trigger bus. Each channel may be also programmed to respond to a particular trigger code arriving on the trigger bus by branching its sequence of test activities. Thus any channel detecting an event during a test can signal all other channels to immediately terminate a current sequence of test activities and branch to another set of test activities. Such a conditional branch capability enables the tester to automatically perform an "if/then" diagnostic test on an IC in which a test result detected at any point during the test determines the future course of the test.

Abstract: A pattern generator for an integrated circuit tester includes an instruction memory storing addressable instructions (INST) and reading out each instruction when addressed by an address (ADDR) supplied as input thereto. An instruction processor receives each instruction read out of the instruction memory and alters the address input to the instruction memory in accordance with the received instruction so that the instruction memory reads out a next instruction. The instruction processor, which includes a conventional return address stack, is capable of executing conventional address increment, call and return instructions. The instruction processor is also capable of executing a temporary return instruction (TEMP) by incrementing its current address output to produce a new return address, by setting its address output to the value of a return address previously saved in the stack, by popping the saved return address from the stack, and by pushing the new return address onto the stack.

Abstract: A programmable and precise voltage-to-current converter (a.k.a. current source) that tracks temperature variations is presented. The voltage-to-current converter is implemented by placing a voltage reference circuit between the bases of the two transistors, or alternatively between a diode and a transistor, in a voltage controlled current source circuit which can be adjusted to track temperature variations. In one embodiment, the voltage reference circuit is a programmable digital-to-analog (D/A) converter. In a second embodiment, the voltage reference circuit is a differential amplifier.

Abstract: A self-balancing temperature control device for an integrated circuit (IC) includes a heat sink attached to the IC having thermomorphic fins or vanes. When the IC increases its heat output, the fins or vanes warm up and change their shape in a manner that increases the rate at which heat is removed from the IC.

Abstract: Noise factor of a radio-frequency device under test (DUT) is determined by driving the input of the DUT with a randomly modulated sine wave and measuring the power of a resulting DUT OUTPUT signal within each of a set of equally-sized frequency bands. The noise factor is computed as a combination of the power of the modulated sine wave within each of a plurality of frequency bands and the measured power of the DUT OUTPUT signal within that same plurality of frequency bands.

Abstract: A semiconductor tester at a first station includes a device handler operating under control of a first computer located at the first station. The handler is provided with a video camera having an output connected to a port of the first computer. A second computer, which includes a display monitor, is located at a second station, which is remote from the first station, and the first and second computers are connected in a computer network. The video camera is employed to acquire an image of the handler and the video camera provides the first computer with video data representative of this image. The video data is transmitted over the computer network to the second computer and is provided to the display monitor, whereby the image acquired by the video camera can be viewed on the display monitor. Information regarding operation of the device handler is transmitted from the second station to the first station.

Abstract: A programmable phase shifter includes a tapped delay line for successively delaying a periodic reference signal to produce a set of phase distributed tap signals. A multiplexer selects one of the tap signals as input to a programmable delay circuit which further delays the selected tap signal to produce an output signal that is phase shifted from the reference signal. A programmable data converter converts input data indicting a desired phase shift between the reference signal and the output signal into data for controlling the multiplexer selection and the amount of delay provided by the programmable delay circuit. The relationship between conversion table input and output data is adjusted so that the period of the output signal has a desired linear relationship to the input data value.

Abstract: An integrated circuit tester produces an output TEST signal following a pulse of a reference CLOCK signal with a delay that is a sum of an inherent drive delay and an adjustable drive delay. The tester also samples an input RESPONSE signal following a pulse of the reference CLOCK signal with a delay that is a sum of an inherent compare delay and an adjustable compare delay. The inherent drive and compare signal path delays within an integrated circuit tester are measured by first connecting a salphasic plane to transmission lines that normally convey signals between the tester and terminals of an integrated circuit device under test. A standing wave signal appearing on that salphasic plane is phase locked to the CLOCK signal so that a zero crossing of the standing wave occurs at a fixed interval after each pulse of the CLOCK signal.

Abstract: An asynchronous integrated circuit (IC) tester includes a set of channels interconnected by a runtime bus. Each channel accesses a separate terminal of an IC device under test (DUT) for carrying out test activities during successive cycles of a test. During each cycle of a test, each channel may transmit a test signal to the DUT, sample a DUT output signal and store sample data representing the logic state of the DUT output signal, and/or compare previously stored sample data to expected patterns to determine if the DUT is operating correctly. Any channel may be programmed to place a MATCH code on the runtime bus when it recognizes, or fails to recognize, a particular logic pattern in the DUT output signal. Other channels may be programmed to pause their comparison activities until they receive the MATCH code over the runtime bus. Thus a DUT output signal event detected by any one channel triggers test activities by other channels.

Abstract: An integrated circuit (IC) tester organizes an IC test into a succession of test cycles, each test cycle being subdivided into four segments. The tester includes a separate tester channel for carrying out a test activity at each IC pin during each segment of the test cycle. The tester also includes a separate pattern generator for each channel. Each pattern generator concurrently generates four vectors at the start of each test cycle. Each vector tells the channel what activity it is to carry out during a separate segment of the test cycle. Each pattern generator includes a low-speed vector memory storing large blocks of vectors at each address and a cache memory system for caching blocks of vectors read out of the vector memory at a low frequency and then reading vectors out in sets of 16 at the higher test cycle frequency. A vector alignment circuit selects from among the cache memory output vectors to provide the four vectors to the channel for the test cycle.

Abstract: Apparatus for supplying a signal after a predetermined time delay comprises circuitry for generating a base delay signal that is synchronized to a stable master oscillator insensitive to changes in at least one environmental variable. A vernier signal delay circuit provides delay increments smaller than those available from the base delay signal, the delay increments being sensitive to said at least one environmental variable. Storage circuitry is provided for storing information related to the duration of the delay increments as function of at least one environmental variable for which correction is to be supplied. Sensing circuitry is provided for sensing the at least one environmental variable for which correction is to be provided to supply a sensed at least one environmental variable.

Abstract: Current consumption of a device under test (DUT) is measured using a tester including a device power supply (DPS) having force and return lines terminating in respective power supply terminals. The DUT is removably received by a load board having contact elements which are in electrically conductive pressure contact with the power supply terminals of the force and return lines and are connected to power supply pins of the DUT. A circuit branch including a bypass capacitor and an nMOSFET is connected between the force and return lines.