Abstract: A physical unclonable function (PUF) can be implemented on a transistor of an integrated circuit device to generate PUF data. A potential difference is supplied across a gate insulator to induce a conductive breakdown in the gate insulator material. Location of the conductive breakdown within the gate insulator and in relation to the source node and drain node can be highly unpredictable, randomly resulting in a higher gate-source current or higher gate-drain current, respectively. The gate-source or gate-drain current can be measured and digitized to generate the PUF data value from the transistor. Moreover, PUF data values generated from multiple transistors can be highly non-correlated and useful for a random data sequence for cryptographic applications and other security applications.

Abstract: Improved differential programming of multiple two-terminal memory cells that define an identifier bit is provided. Differential programming can apply a program cycle to multiple memory cells concurrently, detect a program event for one (or a first group) of the memory cells and disconnect all of the memory cells from a program supply voltage in response to detecting the program event. Moreover, disconnecting the memory cells can be accomplished prior to a duration of the program cycle, serving to mitigate an invalid data result for the identifier bit, as well as reduce power consumption associated with the differential programming. Circuits providing intrinsic suppression of a non-programmed memory cell(s) defining an identifier bit in response to programming of another memory cell (or group of cells) defining the identifier bit are included. Differential programming can reduce power consumption and mitigate or avoid invalid data results for an identifier bit.

Abstract: Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

Abstract: Embodiments of the present disclosure provide intrinsic program suppression of a non-programmed two-terminal resistive switching memory cell of a plurality of memory cells defining an identifier bit, such as a physical unclonable feature (PUF) bit. Differential programming applies a program signal to a plurality of resistive switching memory cells and derives a value for the identifier bit from which cell(s) becomes programmed. However, where more than an expected number of cells become programmed, an invalid value can occur. Disclosed intrinsic program suppression mitigates or avoids the invalid result by very rapidly reducing the program signal to a non-programmed cell(s) in response to another cell(s) becoming programmed. In an embodiment, intrinsic program suppression can be implemented by programming the plurality of memory cells electrically in parallel and shorting second terminals of the plurality of memory cells at a common node.

Abstract: An integrated circuit device can be configured to characterize portions of a resistive switching device array according to one or more operational characterizations. The memory device can store trim instructions defining signal processes for implementing the operational characterizations. Examples of resistive switching device characterizations can include: a physical unclonable feature (PUF) memory characterization, a one-time programmable (OTP) memory characterization, a many-time programmable (MTP) memory characterization, and a random number generation (RNG) memory characterization, among others. The integrated circuit device can characterize portions of the resistive switching device array in response to an instruction from an external host device, exposing control over the selective characterization of the portions of the resistive switching device array to the external host device.

Abstract: Differential programming of multiple resistive switching memory cells defining a bit is disclosed. The differential programming can mitigate invalid data values for the defined bit, referred to herein as an identifier bit. Embodiments of the present disclosure provide for detection of a program event(s) for a portion of resistive switching memory cells defining an identifier bit, and disconnecting a remainder of the memory cells from program supply voltage, prior to a duration of a program cycle. Additionally, the program cycle can be continued for the programmed memory cell(s) to facilitate a robust programming and enhance data longevity. The detection and subsequent disconnection can facilitate proper differential programming and mitigate unwanted program events that lead to invalid identifier bit results, as well as reducing power consumption for a program cycle of resistive switching memory.

Abstract: Fabrication of resistive switching memory devices is herein provided. By way of example, a method for a two-step etch for fabricating a non-volatile resistive memory device is disclosed. In another example, a method for a three-step etch for fabricating a non-volatile resistive memory device is provided. Still other embodiments disclose a method for fabricating a non-volatile metal nitrogen/metal oxygen resistive switching memory device. Further embodiments disclose a method for fabricating a volatile resistive switching selector device. Processes for forming protective spacers in conjunction with fabricating a disclosed resistive memory device are also provided.

Abstract: Techniques for using native and/or previously programmed resistive switching devices as one time programmable memory are discussed. On example method comprises allocating a set of resistive switching devices to be one time programmable memory; determining data to be stored in the set of resistive switching devices; for each resistive switching device of the set of resistive switching devices, assigning one of a first digital value or a second digital value to that resistive switching device, based on the data; and for each resistive switching device assigned the first digital value, permanently programming that resistive switching device via reverse formation.

Abstract: Resistive switching memory cells having filament-based switching mechanisms are provided. By way of example, resistive switching memory cells having resistive filaments constrained to a core of the cell are disclosed. In other examples, methods for fabricating resistive switching memory cells to constrain a conductive filament formed in the resistive switching memory cell to a central portion of core of the cell are disclosed.

Abstract: A field programmable gate array (FPGA) utilizing resistive switching memory technology is described. The FPGA can comprise a switching block interconnect having a set of signal input lines and a set of signal output lines. Respective intersections of the signal input lines and signal output lines can have two resistive switching memory cells, a current differential latch, and a switching transistor (also referred to as a pass gate transistor) arranged in a circuit. Resistance states of the resistive switching memory cells can be programmed to control an output voltage state of the current differential latch. The output voltage state is latched into the current differential latch which can drive a gate of the switching transistor to activate or deactivate the switching transistor, which in turn activates or deactivates an intersection of the FPGA.

Abstract: Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Abstract: A two-terminal resistive switching device (TTRSD) such as a non-volatile two-terminal memory device or a volatile two-terminal selector device can be formed according to a manufacturing process. The process can include forming an etch stop layer that is made of aluminum and can include forming a buffer layer below the etch stop layer and/or between the etch stop layer and a top electrode of the TTRSD.

Abstract: Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification or random number generation. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Abstract: Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

Abstract: A secure integrated circuit comprises a lower logic layer, and one or more memory layers disposed above the lower logic layer. A security key is provided in one or more of the memory layers for unlocking the logic layer. A plurality of connectors are provided between the one or more memory layers and the lower logic layer to electrically couple the memory layer(s) and lower logic layer.

Abstract: Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Abstract: A method for erasing a memory cell includes applying a first erase to memory cells to erase the memory cells, wherein first memory cells are in a weakly erased state in response to the first erase, and wherein second memory cells are in a normally erased state in response to the first erase, thereafter applying a first weak program to the memory cells, wherein the second memory cells enter a programmed state and the third memory cells remain in the erased state in response to the first weak program, and thereafter applying a read to the memory cells to identify the second memory cells, and applying a second erase to the second memory cells to thereby erase the second memory cells.

Abstract: A self-aligned memory device includes a conductive bottom plug disposed within an insulating layer and having a coplanar top surface, a self-aligned planar bottom electrode disposed upon the coplanar top surface and having a thickness within a range of 50 Angstroms to 200 Angstroms, a planar switching material layer disposed upon the self-aligned planar bottom electrode, a planar active metal material layer disposed upon the planar switching material layer and a planar top electrode disposed above the planar active metal material layer, wherein the self-aligned planar bottom electrode, the planar switching material layer, the planar active metal material layer, and the planar top electrode form a pillar-like structure above the insulating layer.

Abstract: Disclosed is a solid state memory having a non-linear current-voltage (I-V) response. By way of example, the solid state memory can be used as a selector device. The selector device can be formed in series with a nonvolatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the nonvolatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

Abstract: Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.