Abstract: Accurate simulation of two-terminal resistive random access memory (RRAM) behavior is accomplished by solving equations including state variables for filament length growth, filament width growth, and temperature. Such simulations are often run in a SPICE environment. Highly accurate models simulate the dynamic nature of filament propagation and multiple resistive states by using a sub-circuit to represent an RRAM cell. In the sub-circuit, voltages on floating nodes control current output while the voltage dropped across the sub-circuit controls growth and temperature characteristics. Properly executed, such a sub-circuit can accurately model filament growth at all phases of conductance including dynamic switching and a plurality of resistive states.

Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

Abstract: A method of forming a non-volatile memory device includes providing a substrate having a surface and forming a first dielectric overlying the surface, forming a first wiring comprising aluminum material over the first dielectric, forming a silicon material over the aluminum material to form an intermix region consuming a portion of the silicon material and aluminum material, annealing to formation a first alloy from the intermix region, forming a p+ impurity polycrystalline silicon over the first alloy material, forming a first wiring structure from at least a portion of the first wiring, forming a resistive switching element comprising an amorphous silicon material formed over the p+ polycrystalline silicon, and forming a second wiring structure comprising at least a metal material over the resistive switching element.

Abstract: A method for forming a semiconductor device including a resistive memory cell includes providing a substrate having an upper surface. A first conductive layer is formed over the upper surface of the substrate. An amorphous silicon layer is formed over the first conductive layer. A surface of the amorphous silicon layer is cleaned to remove native oxide formed on the surface of the amorphous silicon layer. A silver layer is deposited over the amorphous silicon layer after removing the native oxide by performing the cleaning step. The resistive memory cell includes the first conductive layer, the amorphous silicon layer, and the second conductive layer. The surface of the amorphous silicon layer is cleaned to prevent silver agglomeration on the native oxide.

Abstract: A method of forming a vertical interconnect for a memory device. The method includes providing a substrate having a surface region and defining a cell region, a first peripheral region, and a second peripheral region. A first thickness of dielectric material is formed overlying the surface region. A first bottom wiring structure spatially configured to extend in a first direction is formed overlying the first dielectric material for a first array of devices. A second thickness of a dielectric material is formed overlying the first wiring structure. The method includes forming an opening region in the first peripheral region. The opening region is configured to extend in a portion of at least the first thickness of dielectric material and the second thickness of dielectric material to expose a portion of the first wiring structure and to expose a portion of the substrate.

Abstract: A method for forming a semiconductor device including a resistive memory cell includes providing a substrate having an upper surface. A first conductive layer is formed over the upper surface of the substrate. An amorphous silicon layer is formed over the first conductive layer. A surface of the amorphous silicon layer is cleaned to remove native oxide formed on the surface of the amorphous silicon layer. A silver layer is deposited over the amorphous silicon layer after removing the native oxide by performing the cleaning step. The resistive memory cell includes the first conductive layer, the amorphous silicon layer, and the second conductive layer. The surface of the amorphous silicon layer is cleaned to prevent silver agglomeration on the native oxide.

Abstract: This application describes a method of forming a switching device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms a first opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element.

Abstract: A non-volatile memory device includes a plurality of memory units provided in an array, each memory unit having a plurality of resistive memory cells and a local word line. Each resistive memory units has a first end and a second end, the second ends of the resistive memory cells of each memory unit being coupled to the local word line of the corresponding memory unit. A plurality of bit lines is provided, each bit line being coupled to the first end of one of the resistive memory cells. A plurality of select transistors is provided, each select transistor being assigned to one of the memory units and having a drain terminal coupled to the local word line of the assigned memory unit. First and second global word lines are provided, each global word line being coupled to a control terminal of at least one select transistor. First and second source lines are provided, each source line being coupled to a source terminal of at least one select transistor.

Abstract: A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material.

Abstract: A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

Abstract: An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a surface region. A gate dielectric layer overlies the surface region of the substrate. The device includes a MOS device having a p+ active region. The p+ active region forms a first electrode for a resistive switching device. The resistive switching device includes an amorphous silicon switching material overlying the p+ active region and a metal electrode overlies the first metal conductor structure. The metal electrode includes a metal material, upon application of a positive bias to the metal electrode, forms a metal region in the amorphous silicon switching material. The MOS device provides for a select transistor for the integrated circuit device.

Abstract: A method for forming a vertically stacked memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first plurality of memory cells are formed overlying the first dielectric material. Each of the first plurality of memory cells includes at least a first top metal wiring structure spatially extending in a first direction, a first bottom wiring structure spatially extending in a second direction orthogonal to the first top metal wiring structure, and a first switching element sandwiched in an intersection region between the first top metal wiring structure and the first bottom metal wiring structure. In a specific embodiment, the method forms a thickness of second dielectric material overlying the first plurality of memory. A second plurality of memory cells are formed overlying the second dielectric material.

Abstract: A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction.

Abstract: A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode.

Abstract: This application describes a method of forming a switching device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms a first opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element.

Abstract: A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element.

Abstract: A resistive memory device includes a first electrode; a second electrode having a polycrystalline semiconductor layer that includes silicon; a non-crystalline silicon structure provided between the first electrode and the second electrode. The first electrode, second electrode and non-crystalline silicon structure define a two-terminal resistive memory cell.

Abstract: A resistive switching device. The device includes a substrate and a first dielectric material overlying a surface region of the substrate. The device includes a first electrode overlying the first dielectric material and an optional buffer layer overlying the first electrode. The device includes a second electrode structure. The second electrode includes at least a silver material. In a specific embodiment, a switching material overlies the optional buffer layer and disposed between the first electrode and the second electrode. The switching material comprises an amorphous silicon material in a specific embodiment. The amorphous silicon material is characterized by a plurality of defect sites and a defect density. The defect density is configured to intrinsically control programming current for the device.

Abstract: A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material comprising at least an aluminum material is formed overlying the first dielectric material. The method forms a silicon material overlying the aluminum material and forms an intermix region consuming a portion of the silicon material and a portion of the aluminum material. The method includes an annealing process to cause formation of a first alloy material from the intermix region and a polycrystalline silicon material having a p+ impurity characteristic overlying the first alloy material. A first wiring structure is formed from at least a portion of the first wiring material. A resistive switching element comprising an amorphous silicon material is formed overlying the polycrystalline silicon material having the p+ impurity characteristic.

Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.